CODEWITHSUNDEEP
constraintssystem-verilog
Salim
Salim

Reputation: 373

soft constraints not working properly for a bit variable

I have a variable data where I want the last bit to be 1 and the rest of the bits to be 0, and I have written this using soft constraint.

class ABC;
  rand bit [3:0] data;
 
  // This constraint is defined as "soft" 
  constraint c_data {
                       soft data == 0;
                            data[0] == 1;
                    }
endclass
 
module tb;
  ABC abc;

  initial begin
    abc = new;
    abc.randomize();
    $display ("data = %0b", abc.data);
  end
endmodule

I expect the output to be 'b0001, but the actual output is data = 'b1101

Upvotes: 3

Views: 1105

Answers (1)

Silicon1602
Silicon1602

Reputation: 1181

Your issue is caused by the way you define your soft constraint soft data == 0.

Soft contraints will only be satisfied if they don't contradict other (hard) constraints. Your soft constraint says that all bits of data[3:0] must be 0. In your hard constraint, however, you say that data[0] must be 1. Consequently, the soft constraint cannot be satisfied and is ignored.

You can verify this by defining data == 0 as a hard constraint: The randomization will then fail.

To get the behaviour you expect, try to define the class as follows:

class ABC;
    rand bit [3:0] data;

    // This constraint is defined as "soft" 
    constraint c_data {
                        soft data[3:1] == 0;
                        data[0]        == 1;
                       }
endclass

Upvotes: 5

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