How to extract a standalone FPU module from Rocket-Chip Chisel code?

Question

I am working on Rocket Chip Generator, which is a SoC written in Chisel.

My objective is to extract the Floating-Point Unit, in order to synthesize it and study its power consumption/area ...etc. separately from the rest of the SoC.

So I cloned the project and tried to create a dedicated TestHarness where I only instanciate an FPU. This is an example code of what I did (very similar to TestHarness

package freechips.rocketchip.system

import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.devices.debug.Debug
import freechips.rocketchip.diplomacy.LazyModule
import freechips.rocketchip.rocket._

// importing FPU class
import freechips.rocketchip.tile._

class FPUTestHarness() (implicit p: Parameters) extends Module {
  val io = new Bundle {
    val dummyIn    = Bool(INPUT)
    val dummyOut = Bool(OUTPUT)
  }

  // The parameters of the FPU
  val fpu_params = FPUParams(
                              fLen        = 32     // default is 64
                              divSqrt     = false  // default is true
                              // sfmaLatency = 3,  // default
                              // dfmaLatency = 4   // default
                            )

  val fpu = Module(new FPU(fpu_params)(p))

}

The problem is that the implicit parameter p (of type Parameters) doesn't contain something called TileKey, which is needed I don't know where. Apparently the implicit parameter p, passed to FPUTestHarness doesn't contain that information. How can I resolve that? Is it possible to hardcode that somewhere for example?

rocket-chip-new/vsim$ make verilog
mkdir -p /home/mylab/rocket-chip/vsim/generated-src/
cd /home/mylab/rocket-chip && java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar /home/mylab/rocket-chip/sbt-launch.jar "runMain freechips.rocketchip.system.Generator /home/mylab/rocket-chip/vsim/generated-src freechips.rocketchip.system FPUTestHarness freechips.rocketchip.system DefaultConfig"
OpenJDK 64-Bit Server VM warning: Ignoring option MaxPermSize; support was removed in 8.0
[info] Loading settings for project rocket-chip-new-build from plugins.sbt ...
[info] Loading project definition from /home/mylab/rocket-chip/project
[info] Loading settings for project rocketchip from build.sbt ...
[info] Loading settings for project hardfloat from build.sbt ...
[info] Loading settings for project chisel from build.sbt ...
Using addons: 
[info] Set current project to rocketchip (in build file:/home/mylab/rocket-chip/)
[info] Compiling 1 Scala source to /home/mylab/rocket-chip/target/scala-2.12/classes ...
[warn] there were two feature warnings; re-run with -feature for details
[warn] one warning found
[info] Done compiling.
WARNING: An illegal reflective access operation has occurred
WARNING: Illegal reflective access by com.google.protobuf.UnsafeUtil (file:/home/aitsaidn/.sbt/boot/scala-2.12.7/org.scala-sbt/sbt/1.2.7/protobuf-java-3.3.1.jar) to field java.nio.Buffer.address
WARNING: Please consider reporting this to the maintainers of com.google.protobuf.UnsafeUtil
WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations
WARNING: All illegal access operations will be denied in a future release
[warn] Multiple main classes detected.  Run 'show discoveredMainClasses' to see the list
[info] Packaging /home/mylab/rocket-chip/target/scala-2.12/rocketchip_2.12-1.2-SNAPSHOT.jar ...
[info] Done packaging.
[info] Running freechips.rocketchip.system.Generator /home/mylab/rocket-chip/vsim/generated-src freechips.rocketchip.system FPUTestHarness freechips.rocketchip.system DefaultConfig
[info] [0.003] Elaborating design...
List(RocketTileParams(RocketCoreParams(0,true,false,true,true,false,true,false,0,1,false,8,0,true,false,true,0,Some(0),true,true,false,false,false,0,538447876,Some(MulDivParams(8,1,true,true,1)),Some(FPUParams(64,true,3,4))),Some(ICacheParams(64,4,64,32,0,None,None,None,false,64,2,4)),Some(DCacheParams(64,4,64,32,None,None,1,0,17,16,1,64,false,false,false,false,None)),Some(BTBParams(28,14,6,6,Some(BHTParams(512,1,8,3)),false)),0,Some(tile),0,None,None,false))
[error] (run-main-0) java.lang.reflect.InvocationTargetException
[error] java.lang.reflect.InvocationTargetException
[error]         at java.base/jdk.internal.reflect.NativeConstructorAccessorImpl.newInstance0(Native Method)
[error]         at java.base/jdk.internal.reflect.NativeConstructorAccessorImpl.newInstance(NativeConstructorAccessorImpl.java:62)
[error]         at java.base/jdk.internal.reflect.DelegatingConstructorAccessorImpl.newInstance(DelegatingConstructorAccessorImpl.java:45)
[error]         at java.base/java.lang.reflect.Constructor.newInstance(Constructor.java:490)
[error]         at freechips.rocketchip.util.HasGeneratorUtilities.$anonfun$elaborate$1(GeneratorUtils.scala:54)
[error]         at chisel3.core.Module$.do_apply(Module.scala:52)
[error]         at chisel3.Driver$.$anonfun$elaborate$1(Driver.scala:95)
[error]         at chisel3.internal.Builder$.$anonfun$build$2(Builder.scala:343)
[error]         at scala.util.DynamicVariable.withValue(DynamicVariable.scala:58)
[error]         at chisel3.internal.Builder$.$anonfun$build$1(Builder.scala:341)
[error]         at scala.util.DynamicVariable.withValue(DynamicVariable.scala:58)
[error]         at chisel3.internal.Builder$.build(Builder.scala:341)
[error]         at chisel3.Driver$.elaborate(Driver.scala:95)
[error]         at freechips.rocketchip.util.HasGeneratorUtilities.elaborate(GeneratorUtils.scala:59)
[error] Caused by: java.lang.IllegalArgumentException: requirement failed: Key TileKey is not defined in Parameters
[error]         at scala.Predef$.require(Predef.scala:277)
[error]         at freechips.rocketchip.config.View.apply(Config.scala:15)
[error]         at freechips.rocketchip.config.View.apply(Config.scala:12)
[error]         at freechips.rocketchip.tile.HasNonDiplomaticTileParameters.tileParams(BaseTile.scala:37)
[error]         at freechips.rocketchip.tile.HasNonDiplomaticTileParameters.tileParams$(BaseTile.scala:37)
[error]         at freechips.rocketchip.tile.CoreModule.tileParams(Core.scala:90)
[error]         at freechips.rocketchip.tile.HasCoreParameters.$init$(Core.scala:51)
[error]         at freechips.rocketchip.tile.CoreModule.<init>(Core.scala:90)
[error]         at freechips.rocketchip.tile.FPUModule.<init>(FPU.scala:378)
[error]         at freechips.rocketchip.tile.FPU.<init>(FPU.scala:661)
[error]         at freechips.rocketchip.system.FPUTestHarness.$anonfun$fpu$1(FPUTestHarness.scala:71)
[error]         at chisel3.core.Module$.do_apply(Module.scala:52)
[error]         at freechips.rocketchip.system.FPUTestHarness.<init>(FPUTestHarness.scala:71)
[error]         at java.base/jdk.internal.reflect.NativeConstructorAccessorImpl.newInstance0(Native Method)
[error] Nonzero exit code: 1
[error] (Compile / runMain) Nonzero exit code: 1
[error] Total time: 6 s, completed Jul 25, 2019, 7:59:01 PM
/home/mylab/rocket-chip/vsim/Makefrag-verilog:12: recipe for target '/home/mylab/rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfig.fir' failed
make: *** [/home/mylab/rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfig.fir] Error 1

Answer 1

It seems that you use the config as "DefaultConfig". Error log states that you did not specify TileKey parameter in this config. Adding TileKey parameter will resolve the issue. DefaultConfig is defined in rocket-chip/src/main/scala/system/Configs.scala