CODEWITHSUNDEEP
arminterruptstm32
Tarick Welling
Tarick Welling

Reputation: 3255

Is it possible to enable the MemManage_Handler in a STM32 L0

I've written a program which triggers the HardFault_Handler. I believe it is because of a out of memory exception but I want to be completely sure about it. I've seen people disable system interrupt handlers on M3/M4 cores and the reference datasheet states that

(19-Feb-2016) Nested Vector Interrupt Controller

Removed MemManage_Handler, BusFault_Handler,Usagefault _Handler and DebugMon_Handler from Table 53: List of vectors. Updated EXTI_IMR reset value. (19-Feb-2016)

This means that once upon a time the MemManage_Handler existed and that it could be enabled/disabled. But no documentation of this exists. Is it possible to enable this handler?

I personally find it hard to believe that ST has completely removed this handler from the silicon and as such a dormant part of a register should be written to to enable this handler.

Upvotes: 1

Views: 1630

Answers (2)

Colin
Colin

Reputation: 3524

See page 2-17/2-18 of ARM's Cortex-M0+ Devices Generic User Guide, which shows the exceptions native to the processor. This part doesn't have a MemManage exception and all exceptions handled by the fault handler go through to the HardFault.

I suspect that ST's employees made a copy paste error of the vector table at some point from elsewhere, which did have the MemManage_Handler. This also explains the note in the datasheet as they fixed a mistake instead of hiding away a feature.

Upvotes: 1

Bumsik Kim
Bumsik Kim

Reputation: 6623

You can't.

According to Section 3.5 in Managing memory protection unit (MPU) in STM32 MCUs there is no MemMange Fault for Cortex-M0+ devices, it only can trigger HardFault for MPU error.

It is not a ST's decision to remove this feature but Cortex-M0+ simply doesn't have MemMange Fault. I think ST made a copy-and-paste mistake in their documentation.

However, I believe you still can catch MPU errors in the HardFault Handler.

Upvotes: 0

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