CODEWITHSUNDEEP
verilogsignal-processingfpgavivadosynthesis
Alaa Salman
Alaa Salman

Reputation: 107

How can I force vivado to use dsp blocks for all arithmetic operations

I am trying to implement a riscv core on a ZYNQ fpga. I am doing some optimization ways to increase its performance.

How can I force xilinx vivado to use DSPs for any arithmetic operation on my design?

Upvotes: 2

Views: 4945

Answers (1)

fgagnaire
fgagnaire

Reputation: 898

I think that normally Vivado will use DSP evry time it can.

you may want to try to add the attribute "use_dsp" every time you would like to see a DSP, to force vivado to infer it. doc: (search for USE_DSP page 66) https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf

as a side note. In the doc, page 88, there is a good explanation about what Vivado is doing with multiplier.

I do not think that there is way to ask vivado to be "more aggressive" in term of inferring the multiplier. (look at page 44 to see the options)

Upvotes: 2

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