CODEWITHSUNDEEP
vhdlxilinxxilinx-iseseven-segment-display
Fuzzyy
Fuzzyy

Reputation: 73

VHDL Simple Seven Segment Display on Basys2 FPGA board

So I am new to the FPGA world, and I am new to the VHDL language. I tried to light up my seven segment displays, but I always come across with an error. The below code just works on displaying number one on the seven segement when the switch is on and when you flip up a switch an LED turns on. 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity binarycnt is
    Port ( clk : in STD_LOGIC;
              switches : in  STD_LOGIC_VECTOR(7 downto 0);
           LEDs : out  STD_LOGIC_VECTOR(7 downto 0);
           segments : out  STD_LOGIC_VECTOR(7 downto 0);
              anodes : out STD_LOGIC_VECTOR(3 downto 0));
end binarycnt;

architecture Behavioral of binarycnt is
begin
LEDs <= switches;
process (clk, switches)
    begin
        if(switches(0) = '1') then
                segments(1) <= '0';
                segments(2) <= '0';
                anodes(3) <= '0';

        elsif rising_edge(clk) then 
            segments(0) <= '1';
                segments(1) <= '1';
                segments(2) <= '1';
                segments(3) <= '1';
                segments(4) <= '1';
                segments(5) <= '1';
                segments(6) <= '1';
                segments(7) <= '1';
                anodes(0) <= '1';
                anodes(1) <= '1';
                anodes(2) <= '1';
                anodes(3) <= '0';
        end if;
    end process;
end Behavioral;

I tried to do this:

segments <= switches

to light up any light bar with a switch on the seven segment, but I keep getting this error:

Signal segments<1> cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

I am looking for a way to light up the seven segment with switches, and oh, It is my first time using the clock so if my implementation is wrong, I apologise. Any help would be appreciated. Thanks.

Upvotes: 0

Views: 1043

Answers (1)

Matthew
Matthew

Reputation: 13947

Your error message is saying that your synthesiser does not know how to design a circuit that behaves in the same way as your code does. That is what a synthesiser is supposed to do - design a circuit that behaves in exactly the same way as your code does.

What circuit are you expecting? Could you draw it? Have you thought about that? When you design hardware using an HDL, you should know what hardware you are expecting to be synthesised. Not exactly what hardware, but roughly.

Did you simulate this code? Did it behave as you were hoping? Always simulate before you synthesise.

Once you know what hardware you are expecting to be synthesised, you can write your (V)HDL accordingly. You VHDL should conform to one of a small number of templates. There is more about those here.

Upvotes: 1

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