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x86cpuintelinterruptmulticore
VortixDev
VortixDev

Reputation: 1013

How does the CPU decide what core should handle a hardware interrupt?

The question Which processor would execute hardware interrupt in a muticore system and its answers seem to focus on this from the point of view of the operating system, but how does the CPU decide what core to deliver a hardware interrupt to before the OS gets involved?

Upvotes: 3

Views: 763

Answers (2)

Brendan
Brendan

Reputation: 37214

how does the CPU decide what core to deliver a hardware interrupt to before the OS gets involved?

Before the OS gets involved; there is only one CPU running (the rest of the CPUs are stuck in a "wait for startup IPI" state until the OS starts them), and interrupt controller (PIC chips or IO APIC) are configured so that IRQs are sent to the only CPU that is running.

Note: For BIOS; IO APIC is also disabled until the OS enables/configures it, and the firmware uses the old PIC chips (which literally can't be used to decide which CPU to send an IRQ to). For UEFI the firmware mostly doesn't use IRQs (its device drivers poll the device).

After an OS gets involved (not before); the OS configures the IO APIC/s and maybe MSI (Message Signaled Interrupts) and maybe IOMMU to tell the hardware which CPU to send each IRQ to.

There is one special case (the "send to lowest priority CPU" feature) where the chipset decides which CPU to send the IRQ to (based on software setting "task priority" in the local APIC or CR8). Unfortunately this feature may not be supported by the chipset and may not be used by the OS even if it is supported.

Upvotes: 7

zx485
zx485

Reputation: 29022

This is done by the I/O-APIC. APIC stands for Advanced Programmable Interrupt Controller. A quote from the OSDev WiKi:

In addition, there is an I/O APIC (e.g. intel 82093AA) that is part of the chipset and provides multi-processor interrupt management, incorporating both static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts.

An outdated link to a specification can be found here. It describes part of its function as

Provides Multiprocessor Interrupt Management
- Dynamic Interrupt Distribution-Routing Interrupt to the Lowest Priority Processor
- Software Programmable Control of Interrupt Inputs
- Off Loads Interrupt Related Traffic From the Memory Bus

Upvotes: 5

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