CODEWITHSUNDEEP
system-verilogquestasim
Андрей Солодовников
Андрей Солодовников

Reputation: 289

Array of parameters in systemverilog

I try to instantiate array of parameters, e.g.

module top();
    parameter array_size = 10;
    parameter par_array [array_size] = '{array_size{12}};

    initial begin
        $display("%d",par_array[array_size-1]);
    end
endmodule

But when I try to compile this module in questasim, I get this kind of error

-- Compiling module top ** Error: (vlog-13069) parameters_array.sv(3): near "[": syntax error, unexpected '[', expecting ';' or ','.

Search on this subject led me to the following topic and answerer says that systemverilog does allow this kind of construction.
I really don't want use long parameter vector, cause it's lead to new difficulties and this construction is compiling in Vivado (but for the sake of verification I need to use Questa).

Upvotes: 0

Views: 2093

Answers (3)

dave_59
dave_59

Reputation: 42748

An unpacked array parameter requires a data type.

parameter int par_array [array_size] = '{array_size{12}};

Only simple integral parameter can be specified without a data type and just a range.

Do yourself a favor and never rely on implicit data types anywhere.

Upvotes: 1

user5196603
user5196603

Reputation: 1

Try to define an dynamic array type some where:

typedef int int_arr_t[];

Then use the new define type in your module

module #(parameter array_size =12,
                  parameter int_arr_t par_array = '{array_size{12}})

Upvotes: 0

Serge
Serge

Reputation: 12384

parameter arrays are only supported in system verilog. So, make sure that you compile in the system verilog mode (file extension .sv or whatever qualifiers you need).

Also you'd better do int in your case:

parameter int par_array [array_size] = '{array_size{12}};`
----------^^^

Upvotes: 1

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