CODEWITHSUNDEEP
verilog
이호영
이호영

Reputation: 43

How can I fix this "syntax error, unexpected '=' " problem?

I was working on my homework to design the air conditioner by Verilog coding on modelsim, and it keeps failing to compile with a syntax error.

I'm using ModelSim PE Student Edition 10.4a.

module air (rst, power, cooling, dehumidification, ventilation, cl_switch, cl_button, clk, cooler, outdoor_fan, dehumidifier, ventilator, cooling_level);

input rst, power, cooling, dehumidification, ventilation, cl_switch, cl_button, clk;
output reg cooler, outdoor_fan, dehumidifier, ventilator;
output reg [2:0] cooling_level;

parameter OFF = 1'd0;
          ON = 1'd1;

And here's the error message.

** Error: (vlog-13069) C:/Modeltech_pe_edu_10.4a/examples/air.v(8): near "=": syntax error, unexpected '='.

** Error: C:/Modeltech_pe_edu_10.4a/examples/air.v(8): (vlog-13205) Syntax error found in the scope following 'ON'. Is there a missing '::'?

air.v(8) is this

ON = 1'd1;

part. I couldn't figure out what's wrong with my code.

Upvotes: 0

Views: 730

Answers (1)

Oldfart
Oldfart

Reputation: 6259

If you define more then one parameter value, you should separate them with commas:

parameter OFF = 1'd0,
          ON = 1'd1;

Upvotes: 2

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