CODEWITHSUNDEEP
makefilegnu-make
Graznarak
Graznarak

Reputation: 3692

Set different values of a variable for generated targets

I am attempting to create a makefile that generates a target for each file in a directory. Each file would include a list of makefile variable assignments that would then be used by the generated target.

I have it generating targets using eval. I can get the targets to @echo. When I attempt to assign a variable in the file to be used in the target, I don't get what I want. I want it to have the value from the file. I can only figure out how to get the value from the last file or the previous file.

This gives the value of stuff from the previous file:

myvar = $(sort $(basename $(wildcard *.txt)))

.PHONY: all $(myvar)
all: $(myvar)

define target_template =
 stuff := 
 -include $(1).txt
 $(1): ; @echo target $$@ stuffs $(stuff)
endef

$(foreach v,$(myvar),$(eval $(call target_template,$(v))))

This gives me the value from the last file:

myvar = $(sort $(basename $(wildcard *.txt)))

.PHONY: all $(myvar)
all: $(myvar)

define target_template =
 stuff := 
 -include $(1).txt
 $(1): ; @echo target $$@ stuffs $$(stuff)
endef

$(foreach v,$(myvar),$(eval $(call target_template,$(v))))

Each text file has this content:

stuff += mytest<X>

Where <X> is unique per file. Note that I am using += because there may be cases where the included text file includes another file which also adds things to the variable.

Is there a way to get it so that the generated target uses the value of stuff from the associated text file?

I changed the code to this, and it appears to work. Is this something that I shouldn't do?

myvar = $(sort $(basename $(wildcard *.txt)))

.PHONY: all $(myvar)
all: $(myvar)

define target_template =
 $(1):
    $(eval stuff = )
    $(eval include $(1).txt)
    @echo target1 $$@ stuffs $(stuff)
    $(warning $(stuff))
endef

$(foreach v,$(myvar),$(eval $(call target_template,$(v))))

While my solution works, I agree that the accepted solution is better. I am leaving my solution as an example of a worse way to do things.

Upvotes: 0

Views: 67

Answers (1)

Beta
Beta

Reputation: 99084

You don't say what version of Make you're using, but give this a try:

define target_template =
 stuff := 
 -include $(1).txt
 stuff_$(1):= $$(stuff)
 $(1): ; @echo target $$@ stuffs $$(stuff_$(1))
endef

Upvotes: 2

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