CODEWITHSUNDEEP
verilogfpgaconvolutionvivado
Skusku
Skusku

Reputation: 588

Creating multiport block ram in Vivado + Verilog

I want to do convolution in my FPGA. I do have an array, where the image is stored, which then is clocked out to a screen via VGA. I want to compute the convolution the moment a pixel is clocked out, such that I only need multipliers the size of the convolution kernel.

However, I don't know how I can create a block ram, such that I can access for example 9 addresses (if I was using a 3x3 convolution kernel) at the same time. Is that possible in Vivado? I am currently using the Block Ram Generator.

Upvotes: 0

Views: 976

Answers (1)

Oldfart
Oldfart

Reputation: 6259

The best you can do is read two values from two different addresses and for that you have to use dual-ported RAM.

But most of the time you need one port for writing the video data and the second port for reading it.

To read 9 location you have to either:

  • Have 9 different memories
  • Make sure all the data is in one address and make the memory 9 times as wide.

But there is still hope.
In video you get the horizontal pixels one after another. This means that for a 3x3 convolution you can build three small 3-stage pixel pipelines from registers:

enter image description here

(Yes, I put some code in Vivado and use the elaborated schematic for that)

Now you have access to the data of 9 pixels at a time. You could even omit one stage but that might upset your convolution timing.

The final dampener
This looks so simple but for this you need to have access to the data of three video lines at a time. Thus "all" you need to do now is build a system which remember the data for two lines and once you get to line three, re-read the data from the previous two lines and put them with the data of line 3 in the little system shown above. Thus you need at least 2 independent dual-ported memory banks which can each hold one line of video data.

I know this works because I built something just like that last week.

Upvotes: 2

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