CODEWITHSUNDEEP
vhdlxilinxhdlvivado
gxor
gxor

Reputation: 353

VHDL Array from own entity

is it possible to declare an array containing own entities?

I'm trying to get 16 registers (4 bit address) and wanted to access them using an array. I have a "register" entity and a register-manager entity, that is accessed by the ALU with the address:

Register:

entity register is
    port(en    : in STD_LOGIC; 
         d_in  : in STD_LOGIC_VECTOR(7 downto 0); 
         d_out : out STD_LOGIC_VECTOR(7 downto 0));
end register;

Register-Manager:

entity register_manager is
    port(en   : in STD_LOGIC; 
         addr : in STD_LOGIC_VECTOR(3 downto 0); 
         data : in STD_LOGIC_VECTOR(7 downto 0));
end register_manager;

How would I instantiate an array containing these register?

Upvotes: 0

Views: 153

Answers (1)

Gautitho
Gautitho

Reputation: 623

You can use for generate like this :

type t_array is array (0 to 15) of STD_LOGIC_VECTOR(7 downto 0);
signal data_array : t_array;

...

process(clk)
begin

  if rising_edge(clk) then

    for I in 0 to 15 loop
      if to_integer(unsigned(addr)) = I then
        data_array(I)  <= data;
      end if;
    end loop;

  end if;

end process;

for I in 0 to 15 generate

  -- Synthetizer will instantiate 16 registers and each will have a different d_in
  inst_register : register
  port map
  (
    en    => en,
    clk   => clk,
    d_in  => data_array(I), 
    d_out => open           -- Your register_manager has no ouput
  );

end generate;

Note : I introduced a clock because a register without clock in synchronous logic is a bit weird, you should add a reset too. Forgot this note if you are doing some asynchronous logic.

Upvotes: 2

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