gem5: RuntimeError: Cycle found in configuration hierarchy

Question

I'm working on a Processing-in-Memory Simulation by gem5.

I try to link the PIM modules that I made, however, a runtime error with "Cycle found in configuration hierarchy happens".

I do not know when this configuration hierarchy error happens exactly & how to solve it.

I read configuration hierarchy document from gem5 documentation web page several times,

but I couldn't understand how to order the initializations of modules and port bindings to avoid this error.

Also, I don't know how to find the exact code that generates the configuration hierarchy cycle error.

All I can get is just tracebacks of python codes.

If you want to know the configuration code, see the following "very complicated" code from MemConfig.py & traceback.

_kernel = PIMMatrix()
_kernel.bridge.num_bridges = 2
_kernel.bridge.slave[0] = _kernel.xbar.master[0]
_kernel.bridge.master[0] = xbar.slave
_kernel.bridge.slave[1] = xbar.master
_kernel.bridge.master[1] = _kernel.xbar.slave[0]

_kernel.row_sched.instrPort = _kernel.xbar.master[1]
_kernel.row_sched.cmdPort = _kernel.xbar.slave[1]

_kernel.prefix.instrPort = _kernel.xbar.master[2]
for i in range(16):
    _kernel.prefix.memPort[i] = _kernel.xbar.slave[2 + i]

_kernel.A_row_scratch.instrPort = _kernel.xbar.master[3]
_kernel.A_row_scratch.seqPort = _kernel.xbar.slave[18]
_kernel.B_row_scratch.instrPort = _kernel.xbar.master[4]
_kernel.B_row_scratch.seqPort = _kernel.xbar.slave[19]
_kernel.C_row_scratch.instrPort = _kernel.xbar.master[5]
_kernel.C_row_scratch.seqPort = _kernel.xbar.slave[20]
_kernel.C_int_scratch.instrPort = _kernel.xbar.master[6]
_kernel.C_int_scratch.seqPort = _kernel.xbar.slave[21]

num_row_accs = 8
_kernel.num_accs = num_row_accs
row_accs = []
for i in range(num_row_accs):
    row_acc = PIMRowAccelerator()
    num_colrow_accs = 8
    row_acc.num_accs = num_colrow_accs

    row_acc.bridge.num_bridges = 17
    row_acc.bridge.master[0] = row_acc.xbar.slave[0]


    for j in range(16):
        row_acc.bridge.slave[1 + j] = row_acc.xbar.master[j]

        row_acc.colRowSched.instrPort = row_acc.xbar.master[16]
        row_acc.colRowSched.memPort = row_acc.xbar.slave[1]
        row_acc.sorter.instrPort = row_acc.xbar.master[17]
        for j in range(16):
            row_acc.sorter.memPort = row_acc.xbar.slave[2 + j]
        row_acc.ind_hash.instrPort = row_acc.xbar.master[18]
        row_acc.ind_hash.seqPort = row_acc.xbar.slave[18]
        row_acc.val_hash.instrPort = row_acc.xbar.master[19]
        row_acc.val_hash.seqPort = row_acc.xbar.slave[19]

        colrow_accs = []

        for j in range(num_colrow_accs):
            colrow_acc = PIMColRowAcc()
            num_col_accs = 8
            colrow_acc.num_hashers = 8

            colrow_acc.bridge.num_bridges = 17

            colrow_acc.bridge.master[0] = colrow_acc.xbar.slave[0]
            for k in range(16):
                colrow_acc.bridge.slave[1 + k] = colrow_acc.xbar.master[k]

                colrow_acc.colSched.instrPort = colrow_acc.xbar.master[16]
                colrow_acc.colSched.memPort = colrow_acc.xbar.slave[1]

                hashers = []

                for k in range(num_col_accs):
                    hasher = PIMMulHasher()
                    hasher.instrPort = colrow_acc.xbar.master[17 + k]
                    hasher.memPort = colrow_acc.xbar.slave[2 + k]
                    hashers.append(hasher)
                colrow_acc.hashers = hashers

                colrow_accs.append(colrow_acc)

            row_acc.accs = colrow_accs

            for j in range(num_colrow_accs):
                row_acc.accs[j].bridge.slave[0] = row_acc.xbar.master[20 + j]
                for k in range(16):
                    row_acc.accs[j].bridge.master[1 + k] = row_acc.xbar.slave[20 + 16 * j + k]

            for j in range(16):
                row_acc.ind_hash.memPort[j] = row_acc.xbar.master[28 + j]
            for j in range(16):
                row_acc.val_hash.memPort[j] = row_acc.xbar.master[44 + j]

            row_accs.append(row_acc)
        _kernel.row_accs = row_accs

        for i in range(num_row_accs):
            _kernel.row_accs[i].bridge.slave[0] = _kernel.xbar.master[7 + i]
            for j in range(16):
                _kernel.row_accs[i].bridge.master[1 + j] = _kernel.xbar.slave[22 + 16 * i + j]

        for i in range(16):
            _kernel.cache.pim_side[i] = _kernel.xbar.master[15 + i]
        _kernel.cache.mem_side = _kernel.xbar.slave[150]

        for i in range(16):
            _kernel.A_row_scratch.memPort[i] = _kernel.xbar.master[31 + i]
            _kernel.B_row_scratch.memPort[i] = _kernel.xbar.master[47 + i]
            _kernel.C_row_scratch.memPort[i] = _kernel.xbar.master[63 + i]
            _kernel.C_int_scratch.memPort[i] = _kernel.xbar.master[79 + i]

        pim_kernerls.append(_kernel)
    system.pim_kernerls = pim_kernerls

Traceback (most recent call last):
  File "<string>", line 1, in <module>
  File "build/X86/python/m5/main.py", line 457, in main
    exec(filecode, scope)
  File "configs/example/se.py", line 288, in <module>
    Simulation.run(options, root, system, FutureClass)
  File "/mnt/d/gem5/configs/common/Simulation.py", line 614, in run
    m5.instantiate(checkpoint_dir)
  File "build/X86/python/m5/simulate.py", line 120, in instantiate
    for obj in root.descendants(): obj.createCCObject()
  File "build/X86/python/m5/SimObject.py", line 1648, in createCCObject
    self.getCCParams()
  File "build/X86/python/m5/SimObject.py", line 1589, in getCCParams
    value = value.getValue()
  File "build/X86/python/m5/params.py", line 254, in getValue
    return [ v.getValue() for v in self ]
  File "build/X86/python/m5/SimObject.py", line 1652, in getValue
    return self.getCCObject()
  File "build/X86/python/m5/SimObject.py", line 1630, in getCCObject
    params = self.getCCParams()
  File "build/X86/python/m5/SimObject.py", line 1589, in getCCParams
    value = value.getValue()
  File "build/X86/python/m5/SimObject.py", line 1652, in getValue
    return self.getCCObject()
  File "build/X86/python/m5/SimObject.py", line 1630, in getCCObject
    params = self.getCCParams()
  File "build/X86/python/m5/SimObject.py", line 1589, in getCCParams
    value = value.getValue()
  File "build/X86/python/m5/SimObject.py", line 1652, in getValue
    return self.getCCObject()
  File "build/X86/python/m5/SimObject.py", line 1630, in getCCObject
    params = self.getCCParams()
  File "build/X86/python/m5/SimObject.py", line 1589, in getCCParams
    value = value.getValue()
  File "build/X86/python/m5/params.py", line 254, in getValue
    return [ v.getValue() for v in self ]
  File "build/X86/python/m5/SimObject.py", line 1652, in getValue
    return self.getCCObject()
  File "build/X86/python/m5/SimObject.py", line 1634, in getCCObject
    % self.path())
RuntimeError: system.pim_kernerls: Cycle found in configuration hierarchy.

Answer 1

I found the error. I just found some of my custom modules are referencing system as parameter. This makes a configuration hierarchy cycle. Use --pdb option to debug python code.