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Colin
Colin

Reputation: 415

Can enum be made an output in systemverilog?

In verilog, I can do something like this:

module controller (
    input rstb, clk, start,
    output reg [1:0] state, next_state
);
    parameter S_idle = 2'b00, S_1 = 2'b01, S_2 = 2'b11;

    always @ (posedge clk, negedge rstb)
    begin
        if (!rstb) state <= S_idle;
        else state <= next_state;
    end
...
endmodule

But in systemverilog, this will generate an error since I declared state, next_state twice:

module controller (
    input rstb, clk, start,
    output logic [1:0] state, next_state
);
    enum logic [1:0] {S_idle, S_1, S_2} state, next_state;

    always_ff @ (posedge clk, negedge rstb)
    begin
        if (!rstb) state <= S_idle;
        else state <= next_state;
    end
...
endmodule

I suppose I could rename my output ports to state_out, next_state_out and assign them to state, next_state. Is there an easier way to use the enum as an output?

Upvotes: 0

Views: 2749

Answers (1)

dave_59
dave_59

Reputation: 42623

When using user defined types, you should use a typedef and put them in a package so they can be shared amongst the modules that use them. Otherwise you run into type incompatibility assignment errors.

package stuff;
  typedef enum logic [1:0] {S_idle, S_1, S_2} state_t;
endpackage


module controller import stuff::*; (
        input logic rstb, clk, start,
        output state_t state, next_state
    );
        always_ff @ (posedge clk, negedge rstb)
        begin
            if (!rstb) state <= S_idle;
            else state <= next_state;
        end
    ...
 endmodule

Upvotes: 1

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