CODEWITHSUNDEEP
vhdl
CJC
CJC

Reputation: 817

VHDL, passing a partial array of std_logic_vector into an instantiated port map

Consider the following code 

library ieee;
use ieee.std_logic_1164.all;

package pkg is
    type foo is (A, B, C);
    type foo_vector is array (foo) of std_logic_vector;
end package;

Where an entity has the following ports

library ieee;
use ieee.std_logic_1164.all;

entity baz is 
port (iInput : in foo_vector;
      oOutput : out foo_vector);
end;

And it is instantiated by a top module. Now the question is how can i pass only part of the std_logic_vectors of bar into baz instance? Compilation fails when i attempt to use (open)

library ieee;
use ieee.std_logic_1164.all;

entity top is 
end;

architecture rtl of top is 
    signal bar: foo_vector (open) (31 downto 0) := (others => (others => '0'));
begin
    inst : entity work.baz 
    port map (iInput => bar(open)(3 downto 0), --The (open) here does not work
              oOutput => open);    
end;

Upvotes: 0

Views: 1142

Answers (1)

JHBonarius
JHBonarius

Reputation: 11261

You're making your life quite difficult using jagged arrays with unconstrained types that you want to partially assign. I would say: keep it simple. Just use three seperate arrays foovec_A, foovec_B, and foovec_C.

But if you really want it your way, you will need to add logic to send the required signals to a seperate foo_vector. E.g.

library ieee;
use ieee.std_logic_1164.all;

package pkg is
    type foo is (A, B, C);
    type foo_vector is array (foo) of std_logic_vector;
end package;

use work.pkg.all;

entity baz is 
port (iInput : in foo_vector;
      oOutput : out foo_vector);
end;

architecture rtl of baz is begin
end architecture;

entity top is 
end;

library ieee;

architecture rtl of top is 
    use ieee.std_logic_1164.all;
    use work.pkg.all;
    signal bar: foo_vector(open)(31 downto 0) := (others => (others => '0'));
    signal bar_part: foo_vector(open)(3 downto 0);
    signal output : foo_vector(open)(0 downto 0);
begin
    conn : for i in foo generate
        bar_part(i) <= bar(i)(3 downto 0);
    end generate;

    inst : entity work.baz 
    port map (iInput => bar_part,
              oOutput => output);    
end;

will compile (VHDL-2008 mode).

Upvotes: 1

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