CODEWITHSUNDEEP
verilogsequentialflip-flopregister-transfer-level
user
user

Reputation: 37

write a verilog for D FF

enter image description here

I want to write a behavioral verilog code for a FF with the following characteristics as shown in the picture. 

module DFF ( D, CK, RN, Q );
input  D, CK, RN;
output reg Q;

always @ (posedge CK)
begin
if ( RN==1'b0 )
  Q <= RN ; 
if ( RN==1'b1 )
     Q <= D ;
if RN

I DONT KNOW WHAT TO WRITE HERE

end

    );
endmodule

Upvotes: 0

Views: 324

Answers (2)

Hiroto Kagotani
Hiroto Kagotani

Reputation: 400

From your function table, RN seems to be treated as an asynchronous input. In that case, negedge RN should also be added to the sensitivity list. The remaining is the same as @Serge's answer.

always @(posedge CK or negedge RN)
    if (RN == 1'b0)
        Q <= 1'b0;
    else
        Q <= D;

Upvotes: 2

Serge
Serge

Reputation: 12344

There is nothing to write there. It is easier, like the following:

always @(posedge clk)
   if (RN == 1'b0)
       Q <= 1'b0;
   else
       Q <= D;

The only way the Q can be changed is at the posedge of clk. So, your last row in the table is fulfilled here.

The rest is obvious, and you almost got it in your code.

You can use RN as rhs in your code, but it limits flexibility and usually constants are used there.

Upvotes: 1

Related Questions