CODEWITHSUNDEEP
verilog
Guy
Guy

Reputation: 163

Verilog - Getting a mismatch error trying to replicate output of another module

I'm trying to design a fifo that accepts a maximum of N=4 words and has a M=2 bit width of each word. I first designed a 1 bit width word fifo and I'm trying to use it for the wider one. I'm having an issue debugging the line 

single_fifo fArr[M-1:0]({M*{clk}},{M*{reset}},in,{M*{push}},{M*{pop}},out,full_string);

While getting the following error:

ncelab: *E,PCAVDM (./fifo.v,85|27): Vector length of port connection expression (32) in array of instances does not match product of number of instances (2) and port length (1). single_fifo fArrM-1:0;

My code has nothing that's 32 bits long so I'm quite confused by this error.

My code:

 module fifo(clk, reset, in, push, pop, out, full);
   parameter N=4; // determines the maximum number of words in queue.
   parameter M=2; // determines the bit-width of each word, stored in the queue.

   input clk, reset, push, pop;
   input [M-1:0] in;
   output [M-1:0] out;

   wire [M-1:0] full_string;
   output full;
   wire full;

   single_fifo fArr[M-1:0]({M*{clk}},{M*{reset}},in,{M*{push}},{M*{pop}},out,full_string);

   assign full=|full_string;

endmodule

I'll also add the list of ports for single_fifo in case it's required:

module single_fifo(clk,reset,in_bit,push,pop,out_bit,full);
   parameter N=4; // determines the maximum number of words in queue.
   input clk, reset, push, pop;
   input in_bit;
   output out_bit;

   reg [N-1:0] bit_list;
   reg [N-1:0] n; 
   reg out_bit;
   output full;
   reg full;

Sorry if my question seems noobish, I'm still new to verilog. Help will be appriciated!

Upvotes: 0

Views: 878

Answers (1)

dave_59
dave_59

Reputation: 42623

Although you probably meant to use replication {M{clk}} instead of multiplication {M*{clk}}, there is no need for any of this with an array of instances. Verilog automatically replicates the signals you connect to an array of instances so you can just write

single_fifo fArr[M-1:0](clk,reset,in,push,pop,out,full_string);

P.S. I should know because I was responsible for added this feature to Verilog way back in 1990. See section 23.3.3.5 Unpacked array ports and arrays of instances in the IEEE 1800-2017 LRM

Upvotes: 2

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