CODEWITHSUNDEEP
riscv
Ming
Ming

Reputation: 63

Why store instructions have their own format

Load and store instructions have the same requirements for encoding: two registers and a 12-bit immediate. However store instructions (sb, sh, sw) have a dedicated format that is called S-type whereas load instructions use the I-type format which is same as addi instruction.

I don't understand why load and stores don't share the instruction format but stores have a dedicated instruction format only for themselves (S-type).

Upvotes: 6

Views: 873

Answers (1)

Dylan McNamee
Dylan McNamee

Reputation: 1796

I believe the two formats are different to simplify decoding. Looking at the formats of I and S instructions, you'll see:

I: |    imm[11:0]        |  rs1  |  funct3 | rd       | opcode |
S: |  imm[11:5]  |  rs2  |  rs1  |  funct3 | imm[4:0] | opcode |

Load's rd is in the same bit positions of the instruction as in all other instructions that need an rd (I, R, U and UJ formats all put rd in the same place). In contrast, Store instructions don't have a destination register, but rather have an address register and a register whose value we're storing, so the bits needed for rd are instead used as part of an immediate encoding.

If you play with implementing RISC-V yourself (in FPGA, Logisim, or however you choose), you'll see how convenient it is that rd is always in the same place.

To summarize why S instructions have a unique format: they're the only kind of instructions, in a load/store architecture like RISC-V, that do not modify a register's contents. The rest of the instructions do modify a register, so need an rd.

Upvotes: 6

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