Is my understanding of MAKE correct?

Question

Taking the GNU make application as an example, when I create a makefile it is likened to a Visual Studio project file in that it contains the list of files and other items needed to compile an application. The makefile contains the path to the compiler as well as the path to all the files that could possibly be used in the compiling operation. The MAKE application reads the makefile and combines the sources into 1 file which the compiler then reads and converts into the relevant assembly/machine code.

The #include directive is a directive that tells the make file to: "include the contents of this file into this point of the larger file that you're making to feed to the compiler then resume with the current file".

The MAKE application also tells the compiler where to "emit" the result of the compile operation once the compiling is completed. In this regard a Visual Studio .csproj file is technically a XML based makefile for a Microsoft specific MAKE application.

Is this understanding of makefiles correct?

Answer 1

Specifically you are right in that a makefile can be used this way and often are. Generally the make utility resolves dependencies in following rules stating which items (mostly files) depend on others and what steps (e. g. compile operations) are to be taken to fulfill the dependency. Variables and rules within makefiles adhere to the make utility's syntax.

Answer 2

Approximately, yes. However there are numerous details to cavil at.

Taking the GNU make application as an example, when I create a makefile it is likened to a Visual Studio project file in that it contains the list of files and other items needed to compile an application.

That is reasonably close to accurate.

The makefile contains the path to the compiler as well as the path to all the files that could possibly be used in the compiling operation.

The makefile typically does not contain the path to the compiler, though it could. It would contain a list of the files that might be used in the compilation.

The MAKE application reads the makefile and combines the sources into 1 file which the compiler then reads and converts into the relevant assembly/machine code.

This is not very accurate. The details vary, but the aggregation is not done by MAKE, but by the compilers that MAKE invokes. MAKE can be used for other tasks than simple source to machine code translation.

The #include directive is a directive that tells the make file to: "include the contents of this file into this point of the larger file that you're making to feed to the compiler then resume with the current file".

GNU Make (and POSIX Make) supports an include directive to incorporate other fragments of a makefile. The C and C++ compilers recognize the #include directive - and the makefile often needs to be briefed on which headers (included by the #include directive) are needed to compile the program. However, #include is a simple comment in a makefile.

The MAKE application also tells the compiler where to "emit" the result of the compile operation once the compiling is completed.

The makefile contains the information about where the generated code should be placed, and the compiler is told if it needs to know.

In this regard a Visual Studio .csproj file is technically a XML based makefile for a Microsoft specific MAKE application.

That is a reasonable approximation to the description.