CODEWITHSUNDEEP
verilog
user12425978
user12425978

Reputation:

Why does port size doesn't match here in Verilog (16-bit CarrySelectAdder)?

Here I'm designing a 16-bit CarrySelectAdder

Here is the adder file:

module multiplexer2x1_4 (X, I0, I1, S);
   output [3:0] X;   
   input [3:0]  I1;  
   input [3:0]  I0;  
   input S; 
   assign X = (S == 1'b0) ? I0 : I1;
endmodule

module multiplexer2x1_1 (X, I0, I1, S);
   output X;   
   input I1;  
   input I0;  
   input S; 
   assign X = (S == 1'b0) ? I0 : I1;
endmodule

module halfAdder(S,Cout,A,B);
    output S;
    output Cout;
    input A;
    input B;
    xor(S,A,B);
    and(Cout,A,B);
endmodule

module fullAdder(S, Cout, A, B, Cin);
   output S;
   output Cout;
   input  A;
   input  B;
   input  Cin;
   wire   C1;
   wire   C2;
   wire   S1;
   halfAdder h1 (S1,C1,A,B);
   halfAdder h2 (S,C2,S1,Cin);     
   or(Cout, C1, C2);
endmodule 

module rippleCarryAdder(S, C, A, B, Cin);
   output [3:0] S;
   output   C; 
   input [3:0]  A; 
   input [3:0]  B; 
   input    Cin; 

   wire     C0;
   wire     C1;
   wire     C2;

   fullAdder f0(S[0], C0, A[0], B[0], Cin);
   fullAdder f1(S[1], C1, A[1], B[1], C0);
   fullAdder f2(S[2], C2, A[2], B[2], C1);
   fullAdder f3(S[3], C, A[3], B[3], C2);  
endmodule



module carrySelectAdder(S, C, A, B);
   output [15:0] S;  
   output   C;  
   input [15:0]     A;  
   input [15:0]     B; 

   wire [11:0]  S0; 
   wire [11:0]  S1; 

   wire     C0;   
   wire     C1;  
   wire     C2; 
   wire     C3; 
   wire     C4; 
   wire     C5;  
   wire     C6; 
   wire     C7; 
   wire     C8; 

   rippleCarryAdder R1 (S[3:0], C0, A[3:0], B[3:0], 0);

   rippleCarryAdder R2_1 (S0[3:0], C1, A[7:4], B[7:4], 0);     
   rippleCarryAdder R2_2 (S1[3:0], C2, A[7:4], B[7:4], 1);     
   multiplexer2x1_4 mux2 (S[7:4], S0[3:0], S1[3:0], C0);  

   multiplexer2x1_1 mc2 (C3,C1,C2,C0);

   rippleCarryAdder R3_1 (S0[7:4], C4, A[11:8], B[11:8], 0);     
   rippleCarryAdder R3_2 (S1[7:4], C5, A[11:8], B[11:8], 1);     
   multiplexer2x1_4 mux3 (S[11:8], S0[11:8], S1[11:8], C3);  

   multiplexer2x1_1 mc3 (C6,C4,C5,C3);

   rippleCarryAdder R4_1 (S0[11:8], C7, A[15:12], B[15:12], 0);     
   rippleCarryAdder R4_2 (S1[11:8], C8, A[15:12], B[15:12], 1);     
   multiplexer2x1_4 mux4 (S[15:12], S0[11:8], S1[11:8], C6);

   multiplexer2x1_1 mc4 (C,C7,C8,C6);

endmodule

and this is the testbench:

module carrySelectAdder_testBench;
reg [15:0] a;
reg [15:0] b;
wire [15:0] sum;
wire carry;
  carrySelectAdder sl (sum[15:0],carry,a[15:0],b[15:0]);
initial 
begin
$monitor("%b \t %b",sum,carry);
assign a = 16'b1001010110010101;
assign b = 16'b1001010111110101;
$finish;
end
endmodule

it gives me size match error in port 5 in the rippleCarryAdder, What is wrong?

design.sv: L78: warning: Port sizes don't match in port #5 design.sv: L80: warning: Port sizes don't match in port #5 design.sv: L81: warning: Port sizes don't match in port #5 design.sv: L86: warning: Port sizes don't match in port #5 design.sv: L87: warning: Port sizes don't match in port #5 design.sv: L92: warning: Port sizes don't match in port #5 design.sv: L93: warning: Port sizes don't match in port #5

Upvotes: 0

Views: 431

Answers (1)

Silicon1602
Silicon1602

Reputation: 1181

The issue is that you tied the input port of your rippleCarryAdder instance to 0 instead of 1'b0.

0 is an unsized literal constant number here, meaning you did not define the bit-width of this constant. When looking at Section 5.7.1 (Integer literal constants) of the the SystemVerilog LRM, we find that:

The number of bits that make up an unsized number (which is a simple decimal number or a number with a base specifier but no size specification) shall be at least 32. Unsized unsigned literal constants where the high-order bit is unknown (X or x) or three-state (Z or z) shall be extended to the size of the expression containing the literal constant.

Hence, the compiler is interpreting your RTL as if you connected a 32-bit (or more) constant to the 1-bit input port of rippleCarryAdder.

Upvotes: 1

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