CODEWITHSUNDEEP
embedded
Jigar Agrawal
Jigar Agrawal

Reputation: 129

How memory mapped IOs are read by the CPU?

I am learning memory-mapped IOs. I have learned so far that the CPU reads and writes to the specific memory addr to write or read to a certain IO device. In the traditional way, the IO devices used to generate the interrupt and that's how CPU used to know that an IO device is done processing and it has results to be consumed by the CPU.

But in the memory-mapped IO there is no such provision, right? So, according to my knowledge (which doesn't make sense) to read if an IO device has provided any result to CPU or not the CPU needs to go and read the memory every time. Isn't that bad? It is worse than polling, right? because it adds the cycles for reading from the memory.

What am I missing here? Please help.

Upvotes: 1

Views: 133

Answers (1)

Siddharth Kaul
Siddharth Kaul

Reputation: 972

Take and example of my device:

MEMORY {
   IRAM        : origin = 0x0,         len = 0x30000
   CACHE_L2    : origin = 0x30000,     len = 0x10000
   SDRAM       : origin = 0x80000000,  len = 0x1000000
   FPGA_A1     : origin = 0x90000000,  len = 0x1000
   FPGA_A2     : origin = 0xA0000000,  len = 0x1000
   WATCHDOG    : origin = 0xB0000000,  len = 0x1
}

This is for my C6713 DSP. It shares memory with two FPGA's FPGA_1 and FPGA_2 and it share memory with a PowerPC CPU the SDRAM section. This is what can be called an example of memory mapped device. The two FPGA basically handles the ADC conversion, pulsing, digital IO and protections. Lets stick to an ADC.

  • A normal C6713 would process ADC at 50usec. At the same level we would have executed our control loop. Maybe we can push it to 25usec but we are consuming more and more CPU and C6713 would be able to do less and less with each increase in sampling speed.
  • Whereas the FPGA does an ADC conversion per 1usec. So by the time the first control loop starts operation the FPGA has already churned out 50 values. But our control loop doesnt need it all it can go to memory just do a read operation and it has all the values it need.

So by offloading it on a memory mapped device. We have

  • Freed the C6713 from ADC operation. (That is lot of computing power freed)
  • Only with a memory read operation C6713 will have a new value.

So now to have your CPU read back the value you can either schedule a read operation on your CPU making sure it always gets a new value or you can configure your FPGA, in this particular case generate an interrupt every 50 usec making you CPU interrupt driven.

So in short no it is not bad as you gain a lot by offloading such tasks from CPU and free up lot of computing power. In process of doing so you also simplify your system.

Hope this helps.

Upvotes: 1

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