Reputation: 63
I wrote this Verilog code. The inner module is an 8-bit mux, and the top module is used to test the mux. It should display 11110000
, but it displayed xxxxxxxx
every time. How do I fix this?
module testbench;
reg CLK;
test mytest(CLK);
initial begin
CLK = 1'b0;
#10
CLK = 1'b1;
end
endmodule
module test(CLK);
input CLK;
reg [7:0] in0,in1;
reg sel;
wire [7:0] out;
mux myux(in0,in1,sel,out);
always @(posedge CLK) begin
sel = 1'b0;
in0 = 8'b11110000;
$display("%b",out);
end
endmodule
This is the mux
module:
module mux(in0,in1,sel,out);
input sel;
input [7:0] in1,in0;
output [7:0] out;
reg out;
always @(in0,in1,sel) begin
if(sel == 1'b0) begin
out = in0;
end
else begin
out = in1;
end
end
endmodule
Upvotes: 0
Views: 66
Reputation: 62236
The problem is that you did not run your simulation long enough. You only ran it for one clock cycle. Here is one way to change your testbench
module to run many clock cycles:
module testbench;
reg CLK;
test mytest(CLK);
initial begin
CLK = 1'b0;
forever #10 CLK =~CLK;
end
initial #1000 $finish;
endmodule
I now see output like this:
xxxxxxxx
11110000
11110000
11110000
11110000
Also, I got a compile error with your code. In your mux
module, you should change:
reg out;
to:
reg [7:0] out;
Upvotes: 2