CODEWITHSUNDEEP
verilogsystem-verilog
toiavalle
toiavalle

Reputation: 434

How to write to a txt log file in a verilog simulation testbench

I apologize if this is a stupid question. I'm a student taking a class in SystemVerilog but the board I was supposed to use has a broken VGA port and I can't get it fixed or replaced due to the whole coronavirus situation. I'm trying to use a VGA simulator so I can do my assignments for the class, but I have very limited experience with Verilog and I'm having a hard time setting up the simulator. If anyone could point me in the right direction either on how to set up this simulator or what other simulator to use I would really appreciate

I'm trying to use a VGA simulator (https://ericeastwood.com/blog/8/vga-simulator-getting-started) but to use it I need to produce a log file (they only provide the code for VHDL - this code is in the link above if it helps). So I need to be able to, in the test bench, write values of my variables and the current simulation time to a txt file on each clock cycle. Is this possible in SystemVerilog? How should I go about it?

Upvotes: 1

Views: 3004

Answers (1)

Justin N
Justin N

Reputation: 911

You can use $fwrite, e.g.:

integer fd;
initial fd = $fopen("log.txt", "w");

reg [3:0] val;
reg sim_done = 0;

...

always @(posedge clk) begin
  $fwrite(fd, "%t %x\n", val);

  if (sim_done) begin
    $fclose(fd);
    $finish;
  end
end

Upvotes: 1

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