CODEWITHSUNDEEP
verilogsystem-verilogvivadotest-bench
abhijith
abhijith

Reputation: 11

Why is the simulation stuck in Vivado?

I tried to develop a spare memory code, but the simulation got stuck in Vivado. I cannot exactly say whether it is stuck or not, but the simulation is not running. I've attached the image for the problem I'm unable to clearly express. The testbench of the code goes here. While trying to get a simulated waveform, Vivado is not giving a simulation, whereas it is fully working in Icarus Verilog, and the simulation waveforms are clear in GTK wave.

module trial_tb;
    
      reg clk;
      reg rst_n;
      reg bist_enable;
      reg we;
      reg [5:0] wraddr;
      reg data_in;
      reg re;
      reg [5:0] rdaddr;
    
      wire data_out; 
      wire repair_fail;
      wire repair_finish;
    
      integer m;
      integer idx;
    
      SRAM_repair uut (clk, rst_n, bist_enable, we, wraddr, data_in, re, rdaddr, data_out, repair_fail, repair_finish);
    
      initial
      begin
        clk = 0;  
        rst_n <= 0;
        bist_enable <= 0;
        rdaddr <= 'b0;
        wraddr <= 'b0;
        we <= 1'b0;
        re <= 1'b0;
        data_in <= 1'b0;
        
        #5.0 rst_n <= 1;
        #5.0 bist_enable <= 1;
        #52.9 bist_enable <= 1'b0;
        
        
        we <= 1'b1; 
        data_in <= 1'b0;
       
        for ( m=0 ; m<=32; m=m+1) begin
        wraddr <= m;
        #0.2;
        end
    
        data_in <= 1'b1;
        
        for ( m=33 ; m<=63; m=m+1) begin
        wraddr <= m;
        #0.2;
        end
            
        #0.2;
        we <= 1'b0;
        re <= 1'b1;
    
        for ( m=0 ; m<64; m= m+1) begin
        rdaddr <= m;
        #0.2;
        end
                          
      end
    
      initial 
      begin
        $dumpfile ("SRAM_repair.vcd");
        $dumpvars( 0, trial_tb);
       // $dumpvars( 0, trial_tb.uut.i_bisr_controller.fcr\[0\]);
       // $dumpvars( 0, trial_tb.uut.i_bisr_controller.fcr\[1\]);
      //  $dumpvars( 0, trial_tb.uut.i_bisr_controller.fcr\[2\]);
      //  $dumpvars( 0, trial_tb.uut.i_bisr_controller.fcr\[3\]);
      //  $dumpvars( 0, trial_tb.uut.i_bisr_controller.fcr\[4\]);
     //   $dumpvars( 0, trial_tb.uut.i_bisr_controller.fcr\[5\]);
        #90 $finish;
      end
            
      always #0.1 clk = ~clk;
    endmodule

vivado gui

Upvotes: 1

Views: 5008

Answers (1)

toolic
toolic

Reputation: 62037

I suspect you did not use a proper timescale for the delays in your testbench. From IEEE Std 1800-2017, section 22.7 `timescale:

If there is no `timescale specified or it has been reset by a `resetall directive, the default time unit and precision are tool-specific.

When not specified, my simulator defaults to:

`timescale 1ns/1ns

I see the simulation hang at time 0, as I think you do. Since the time precision is the same as the time unit (both are 1ns for me), the 0.1 delay for clk is rounded down to 0, causing an infinite loop in the clk always block.

I fixed this by adding this explicit timescale before the module:

`timescale 1ns/100ps

This sets the precision less than the unit, allowing the clk to toggle properly.

The discrepancy you see between Vivado and Icarus is likely a result of different timescales being used. To see what timescale is in effect, add this code to your testbench:

initial $printtimescale;

Upvotes: 5

Related Questions