CODEWITHSUNDEEP
if-statementverilogfpga
sujeto1
sujeto1

Reputation: 411

Are these two verilog sentences equivalent, do they take the same cycles?

I want to know if these two codes would be doing the same? And what is the practical difference between them? If they are doing the same operation, is the second case faster than the first case?

In the first case, because I have to wait until it comes out to the "cycle statement" to recognize the rising of the flag "modi_varx_f" and "modi_vary_f" in order to "activate" in the next cycle and operate the increase of the variable, then it's slower than to do it at once as in the second case that seems to "activate" and run the operation within the same cycle.

  1. First case:
always@(posedge clk or negedge rst) begin
    if (~rst) begin
        modi_varx_f = 0;
        modi_vary_f = 0;
    end
    else if (cond1) begin
        modi_varx_f = 1; // increase variable x on 1.
        modi_vary_f = 1; // add 3'd6 to variable.
    end
end

always@(posedge clk or negedge rst)
    if (~rst) 
        varx  = 0;
    else if (modi_varx_f)
        varx = varx + 1;
end  

always@(posedge clk or negedge rst)
    if (~rst) 
        vary  = 0;
    else if (modi_vary_f)
        vary = vary + 3'd6;
end
  1. Second case:
always@(posedge clk or negedge rst) begin
    if (~rst) begin
        varx = 0;
        vary = 0;
    end
    else if (cond1) begin;
        varx = vary + 1; 
        vary = vary + 3'd6;
    end
end

Upvotes: 0

Views: 91

Answers (1)

Serge
Serge

Reputation: 12384

just to summarize the comment stream. In general, you can collapse multiple sequential always blocks into one without loosing functionality. I guess that you made a mistake in the second example and used varx = vary + 1; while in the first case you used varx = varx + 1;. This makes the difference.

However, if the second example uses varx, than both are equivalent.

Since you used sequential elements (flops with asynchronous reset) in your examples, you should have used non-blocking assignments there, according to industry-wide practices. And the right answer for collapsing should look like this:

always@(posedge clk or negedge rst) begin
    if (~rst) begin
        varx <= 0;
        vary <= 0;
    end
    else if (cond1) begin;
        varx <= varx + 1; // << varx
        vary <= vary + 3'd6;
    end
end

Upvotes: 1

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