CODEWITHSUNDEEP
vhdlxilinx
marverix
marverix

Reputation: 7705

Generate State Machine graph from VHDL code?

Is there any quite good tool to generate State Machine graph from VHDL code? I'm using Xilinx ISE Webpack. Cheers!

Upvotes: 1

Views: 4464

Answers (2)

vermaete
vermaete

Reputation: 1373

Modelsim SE (and DE?) have these kind of things. But, not for free :-(

Upvotes: 1

Josh
Josh

Reputation: 3655

Active HDL has a feature called "Code2Graphics" which supports this. Additionally, some synthesis tools (typically ones you would have to pay for) also support this.

Note that an RTL view is more commonly available in synthesis tools (such as XST).

Upvotes: 4

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