CODEWITHSUNDEEP
cachingmemorycpu
Livia Mitrică
Livia Mitrică

Reputation: 43

Cache memory design - address decoding

I was given the following problem:

A CPU generates 32 bit addresses for a byte addressable memory. Design an 8 KB cache memory for this CPU (8 KB is the cache size only for the data; it does not include the tag). The block size is 32 bytes. Show the block diagram, and the address decoding for direct mapped cache memory.

I determined that:

enter image description here

Is my solution correct? How should I do the decoding?

Upvotes: 0

Views: 416

Answers (1)

Sebastian Kurella
Sebastian Kurella

Reputation: 11

The numbers seem correct, however it is always worth pointing out in your solution that you're taking cache associativity under account. Specifically, 32-8-5=19 is only valid when the cache is directly mapped.

The decoding part is nicely illustrated in your drawing – it's simply the act of taking 32 bits of the address as used by the CPU apart into the tag, index, and offset fields.

Upvotes: 1

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