CODEWITHSUNDEEP
vhdlghdl
nulleight
nulleight

Reputation: 852

ghdl elaborate an entity in a package

I have a VHDL program and I can't elaborate it with GHDL, because the entity to elaborate is in a package. How do I elaborate an entity in a package with GHDL?

EDIT:

Thanks for the answers, after some time I figured out that the code in a package was something like an interface and we are supposed to implement this component ourselves and I falsely assumed that it was complete. Sorry for the wrong question, I am new to VHDL and am learning the ropes and couldn't find any explanation on google since my assumptions were wrong.

Upvotes: 2

Views: 1690

Answers (2)

bmk
bmk

Reputation: 14147

I'm quite confident that the VHDL standard does not allow to declare entities in packages. Only components, subprograms, signals, constants, types and subtypes can be declared there.

Upvotes: 5

Josh
Josh

Reputation: 3655

I don't believe it is legal to put an entity inside a package. You can put types, subtypes, constants, signals, files, aliases, component, attributes and groups into a package.

So you can put a component definition, which can map to an entity, inside of a package. This is convenient so that you could put a component in a single shared package instead of putting it in the architecture of every design unit that needs to use the functionality of the entity.

Upvotes: 6

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