CODEWITHSUNDEEP
typesenumssystem-verilog
Wilderness
Wilderness

Reputation: 1399

System Verilog Enum Type Assignment

I have a generic module in my library which is used multiple times at different places in the design.

    module generic #(
      parameter WIDTH = 1
    ) (
      input  logic [WIDTH-1:0] a,
      output logic [WIDTH-1:0] z
    );
    
    some function...
    
    endmodule

This is used in the design like so, where my_type_t is a typedef enum logic type defined elsewhere:

    my_type_t ope, res;
    generic #(
       .WIDTH ($bits(ope))
    ) ope_res (
      .a (ope),
      .z (res)
    );

When I compile, I get lint warnings in VCS:

    Warning-[ENUMASSIGN] Illegal assignment to enum variable
    ...
      Only expressions of the enum type can be assigned to an enum variable. 
      The type logic [WIDTH-1:0] is incompatible with the enum 'my_type_t'
      Expression: z
      Use the static cast operator to convert the expression to enum type.

Is there an easy way to fix this? The generic module is used for different types, so that has to be a non-type module.

Upvotes: 1

Views: 4069

Answers (1)

dave_59
dave_59

Reputation: 42623

You better have good reason for casting in an out of an enum type. You can work around the error using the streaming unpack operator

generic #(
   .WIDTH ($bits(ope))
) ope_res (
  .a (ope),
  .z ({>>{res}})
);

The proper way to fix this is making generic using a parameterized type.

module generic #(
  parameter WIDTH = 1, type T = logic [WIDTH-1:0]
) (
  input  logic T a,
  output logic T z
);

// some function...

endmodule

module ...
 my_type_t ope, res;
 generic #(
   .T (my_type_t)
 ) ope_res (
  .a (ope),
  .z (res)
 );
endmodule

Upvotes: 5

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