Reputation: 63
i was compiling a kernel module thermal.c at an ARCH linux distro using Makefile
Makefile:
obj-m += thermal.o
all:
make -C /lib/modules/$(uname -r)/build/ M=$(PWD) modules
clean:
make -C /lib/modules/$(uname -r)/build/ M=$(PWD) clean
the make command output is:
make -C /lib/modules//build/ M=/home/user/dir modules
make[1]: *** /lib/modules//build/: No such file or directory. Stop.
make: *** [Makefile:4: all] Error 2
uname -r
output : 5.6.8-arch1-1
Upvotes: 4
Views: 20939
Reputation: 28935
make expands the recipes before passing them to the shell. In your case make replaced $(PWD)
by the value of the make variable named PWD
(correct) but it also replaced $(uname -r)
by the value of the make variable named uname -r
. As there was no such make variable defined, the result was the empty string. Using $$(uname -r)
solves the problem because make expands it as $(uname -r)
, exactly what you want to pass to the shell.
In summary, you must escape the $
you want to preserve from the make expansion by doubling them:
all:
make -C /lib/modules/$$(uname -r)/build/ M=$(PWD) modules
clean:
make -C /lib/modules/$$(uname -r)/build/ M=$(PWD) clean
Upvotes: 2