Reputation: 257
I need to convert an unsigned char image (640x480x1) or smaller to a float image for processing. I can't do fixed-point computation in this case due to the problem complexity. I currently use the neon unit in a two-step process. The neon can convert an integer to an float fairly fast, but not an unsigned char to float.
1) convert unsigned char image to integer image using a LUT (no generic casting since I know the range) 2) use the neon to convert from integer to float
This process take roughly 10-15 ms just to prepare the image for processing.
I could also use a LUT in step one that converts directly to a float. However, I have found that doing this takes longer than using the NEON from integer to float. So I'd actually like to use the NEON to convert directly from an unsigned char to float and get rid of step 1.
Does anyone know of a better way?
Upvotes: 1
Views: 2031
Reputation: 129
Another more compact approach would be:
; load stuff into D4 (e.g. {6,7,8,9,a,b,c,d})
vmovl.u8 q1, d4
vmovl.u16 q0, d2
vmovl.u16 q1, d3
; Now Q0 should contain {6,0,0,0,7,0,0,0,8,0,0,0,9,0,0,0}; similarly for Q1
; Interpret them as (little-endian) 32-bit ints and convert them to floats
vcvt.f32.u32 Q0,Q0,#0
vcvt.f32.u32 Q1,Q1,#0
; And save them somewhere
Upvotes: 1
Reputation: 33592
EDIT: "unsigned char to int conversion" merely involves adding some zero bytes at the right places. The obvious way is to perform the necessary shifts, then VDUP to clear a vector, and VMOV.U8 four times. That seems a bit slow.
The faster way is probably with VTBL:
; load stuff into D4 (e.g. {6,7,8,9,a,b,c,d})
; D5 already contains {0,-1,-1,-1,1,-1-1-1}
; D6 already contains {2,-1,-1,-1,3,-1-1-1}
; D7 and D8 are similar...
vtbl.8 D0,{D4},D5
vtbl.8 D1,{D4},D6
vtbl.8 D2,{D4},D7
vtbl.8 D3,{D4},D8
; Now Q0 should contain {6,0,0,0,7,0,0,0,8,0,0,0,9,0,0,0}; similarly for Q1
; Interpret them as (little-endian) 32-bit ints and convert them to floats
vcvt.f32.u32 Q0,Q0,#0
vcvt.f32.u32 Q1,Q1,#0
; And save them somewhere
Of course, you can specify #8
instead of #0
to divide everything by 256.
I didn't see a quadword version of VTBL, but such a rewrite wouldn't be too hard to do. The obvious extension is to do a quadword load in to Q2 = {D4,D5}, and repeat the process specifying D4 instead of D5 (or use more registers to avoid data dependency stalls).
Other optimizations include preloading the cache (I forget what the corresponding ARM instructions are). In general, you'll probably find it difficult to beat Accelerate.framework without putting in significant effort.
Upvotes: 1