CODEWITHSUNDEEP
cachingmemory-managementpaging
Dan
Dan

Reputation: 627

Relation between memory paging and CPU cache lines

This is my understanding of Paging and CPU Cache lines:

Paging is memory management scheme by which a computer stores and retrieves data from hard disk. Paging is not related to CPU load/store.

Cache line is the size in which data is stored and retrieved between memory and CPU registers. Cache line is not related to hard disk load/store.

My questions are:

1- Is my understanding mentioned above correct?

2- When a Page fault occurs, how does the OS know where to look for in hard disk for the data to load? Say I need to load address 0x123 from memory but this address is not paged yet, where is 0x123 data located on disk?

Upvotes: 3

Views: 1054

Answers (1)

user123
user123

Reputation: 2884

You are not correct for most of what you say. Paging is partially implemented by the CPU and partially by the OS.

Paging is related to RAM and is used mostly for better memory management.

Nowadays, there is not much need for what is called (in Linux) swap space. The swap space is used to store pages from RAM on the hard disk temporarily when the OS lacks RAM space. Since RAM is more and more available at lower cost. I think it is pretty rare that swap space will be used.

As for caches, there are several caches in the CPU. The main cache is known to have several levels like L1, L2 etc. It stores pages that have higher chance of being reused. It is managed by the CPU and invisible to the OS.

The TLB is another cache which is used to store the translation of virtual adresses to physical adresses. This is used so that the translation doesn't need to be redone every time a certain virtual adress is accessed in code. It is managed by the CPU as well. The TLB must be flushed when changing the executing process.

The paging memory management scheme is used to manage RAM memory not the hard disk.

On x86, there is a control register (CR3) which is used to store the address of the first table used for virtual address translation. Once paging is enabled in your processor by setting a few flags in its control registers (CR0, CR4), it will start using the Memory Management Unit (MMU) to translate the virtual adresses you reference to physical adresses. Before outputing a value on the address bus, the value will go through the MMU to be translated. The MMU will look at the address referenced by the CR3 register which is in RAM and initialized by the OS at boot or during execution.

As an example, for x86-64 (the most modern) the paging scheme is called by intel IA-32e. It has 4 levels of paging called PLM4, PDPT, PDT and PT (see https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf).

In this paging scheme, the virtual address will have 64 bits but only 48 bits will be used. 9 bits are used as offset for each 4 tables. The last 12 bits (least significant) will be used as offset in the physical page itself.

If you have address 0x123. This gives

0x00 00 00 00 00 00 01 23

or in binary

Not used             Offset in pml4  Offset in pdpt  Offset in pdt
0000000000000000     000000000       000000000       000000000
Offset in pt   Offset in page
000000000      0001 0010 0100

So you would reference entry 0 in pml4, 0 in pdpt, 0 in pdt and 0 in pt. You would have an offset of 0x123 in the page referenced by these entries.

Upvotes: 2

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