CODEWITHSUNDEEP
veriloghardwarevivado
ProgrammingGuy
ProgrammingGuy

Reputation: 41

Calling a Module in Verilog

I just started learning hardware programming using Verilog, and I feel lost because I can't understand what errors mean. Here, I am calling the module reg31

module nbit_register(input clk, input [31:0]in, input reset, input L,
input load, input shift, output reg[31:0] out);
always@(*)begin
if(load==1) 

  reg32 add(clk, in, reset,L, out);
  
   else
        out={ in[30:0],1'b0};
   end
    
   endmodule

But, I get this error:

error: syntax error near "reg32"

This is what the module looks like

module reg32(
    input clk,
    input [31:0] in,
    input rst,
    input  L,
    output  [31:0] out
    );

Can someone point out the mistake here?

Upvotes: 2

Views: 5419

Answers (1)

Light
Light

Reputation: 1306

Because you want to "select" and make module reg32 "work" in a if branch.

Imaging a cell phone PCB board. The speaker unit is just out there, even if it's in silent mode. So instantiate reg32 separately, then use your own logic to deal with the nets connected to reg32.

wire [31:0] add_out;
reg32 add(clk, in, reset,L, add_out); // here the 4 inputs are connected to top inputs
                                      // directly. but if you want, you can use 'load'
                                      // to control them similar to the code below.

always@(*)begin
  if(load==1)
    out = add_out;
  else
    out = { in[30:0],1'b0};
  end

If you're mainly working on software, you need to be familiar to thinking in a "hardware" way.

Upvotes: 2

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