CODEWITHSUNDEEP
systemc
Jomon
Jomon

Reputation: 1

Need help to implement an interrupt controller simulator which handles the ISR

I am on the implementation of an interrupt controller simulator, which will take signals from other rest of the HW modules in simulation and run the ISR.

Below is the SystemC code roughly made to get the concept clear. In this case, we need ISR to be handled in a way that, even if the FW_main is stuck inside while(1) loop.

With the below implementation the context is inside FW_main loop only. Adding a wait in FW_main is not the one we want. We need the correct interrupt controller functionality. Any ideas to get rid of this problem?

SC_MODULE (processor)
{
    sc_in < bool > interrupt;

    void ISR(void)
    {
        cout << "i am in ISR\n";
    }
    
    void FW_main(void)
    {
        while(1)
        {
            cout << "i am in FW_main\n";
        }
    }
    
    SC_CTOR (processor) 
    {
        SC_METHOD(ISR);
        sensitive << interrupt;
        SC_THREAD(FW_main);
    }
    
};

Upvotes: 0

Views: 161

Answers (1)

ASICcoder
ASICcoder

Reputation: 99

Unfortunately SystemC processes are cooperative, not preemptive. Even the SystemC kernel can't step in and suspend the FW_main method.

No processor system / FW truly gets stuck in a while loop this way. Any instruction set simulator must walk the time in steps on some sort of strobes or events, ideally clock edges.

Functional representation of a system you are trying to model would look something like follows.

SC_MODULE (processor)
{
    sc_in < bool > clk;
    sc_in < bool > interrupt;

    void ISR(void)
    {
        cout << "i am in ISR\n";
    }
    
    void FW_main(void)
    {
        cout << "i am in FW_main\n";
    }
    
    SC_CTOR (processor) 
    {
        SC_METHOD(ISR);
        sensitive << interrupt;
        SC_METHOD(FW_main);
        sensitive << clk;
    }
    
};

There are two problems in above code I suggested. First, you probably don't want an actual clock signal that needs toggling externally or any sense of time at all for that matter. Second, in a single core processor system, ISRs and FW_Main aren't really parallel in nature. A more realistic implementation of what you are trying to model would be as follows.

SC_MODULE(processor)
{
    sc_in < bool > interrupt;

    void ISR(void)
    {
        cout << "i am in ISR\n";
    }
    
    void FW_main(void)
    {
        if(interrupt.read())
        {
            ISR();
        }

        cout << "i am in FW_main\n";

        next_trigger(SC_ZERO_TIME, interrupt);
    }
    
    SC_CTOR (processor) 
    {
        SC_METHOD(FW_main);
    }
    
};

The next_trigger(SC_ZERO_TIME, interrupt) statement makes the FW_main emulate while(1) while also being sensitive to interrupt input.

Upvotes: 0

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