CODEWITHSUNDEEP
veriloghdlvivado
Jake Yoon
Jake Yoon

Reputation: 138

Verilog How to change wire by bit with clock?

module clks(
    input clk,
    output [15:0] led
    );
    
    wire div2, div4, div8;
    reg [2:0] count = 0;
    assign div2 = count[0];
    assign div4 = count[1];
    assign div8 = count[2];
    always @(posedge clk) count = count + 1;
endmodule

How can I turn on each led (I have 15 leds) using clock? I'm really having trouble finding helpful resources online

initial begin
        case({count})
        2'b00:
            led = 15'b000000000000001;
        2'b01:
            led = 15'b000000000000010;
        ...

        endcase
    end

This didn't work. Or could I do something like this?

led = led + 1;

Upvotes: 1

Views: 690

Answers (2)

Serge
Serge

Reputation: 12354

I guess that 'by using clock' means changing the led every clock cycle, right? Also it looks like you are trying to encode the led sequentially. In this case you can do the following:

  1. you need to reset your lead to an initial value, sey 15'b1;

  2. every clock cycle you can just shift it left by one. You should not do it in an initial block (though there is a technical way to do so). Use always blocks:

Here is an example:

module clks(
    input clk,
    input reset,
    output reg [15:0] led
    );

   always @(posedge clk) begin
      if (reset == 1) 
         led <= 15'b1;
      else
         led <= led << 1;
   end
endmodule

In the above case '1' will travel through all bits of led over 15 clock cycles once. 'led' will become '0' after this. You have to make sure that it becomes '1' again if you want to continue in cycles.

Another possibility is to initialize 'led' in the always block, but it is not always synthesizable. YOu do not need a reset signal here.

initial led = 15'b1;
always @(posedge clk) led <= led << 1;

Upvotes: 1

Rich Maes
Rich Maes

Reputation: 1222

In your sample code above, you defined count as 3 bits, but your case statements are 2 bits wide. Also, you don't want the initial statement, rather use an always statement.

always @ (count)
begin
case(count)
3'b000 : led = 15'b000_0000_0001;
3'b001 : led = 15'b000_0000_0010;
...
endcase
end

Upvotes: 2

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