CODEWITHSUNDEEP
makefile
AProgrammer
AProgrammer

Reputation: 52274

Rebuilding when a variable change

Some make variables have an effect on the generation of the targets and thus one may want to rebuild if their value changes, for instance because they were specified explicitly on the command line. With GNU Make, it is relatively easy to do. For instance one can do this:

CHECK_CFLAGS:=.last-cflags.$(shell echo $(CFLAGS) | md5sum | awk '{ print $$1 }')

foo.o: foo.c $(CHECK_CFLAGS)

.last-cflags.%:
    -rm .last-cflags.*
    touch $@

(Obviously if you are using target specific value, things become more complex). Is there a way to achieve the same desired effect with standard (POSIX) Make? If not, with the BSD variant of Make?

Upvotes: 4

Views: 692

Answers (1)

MadScientist
MadScientist

Reputation: 100781

If you can assume GNU make 4.0 or above, you can use the != assignment operator which was implemented in GNU make for portability with BSD make.

From the GNU make manual:

The shell assignment operator '!=' can be used to execute a shell script and set a variable to its output. This operator first evaluates the right-hand side, then passes that result to the shell for execution. If the result of the execution ends in a newline, that one newline is removed; all other newlines are replaced by spaces. The resulting string is then placed into the named recursively-expanded variable.

Note there is one subtle difference between != and := $(shell ...): in the former the resulting variable is a recursive variable which means it will be re-expanded on use. So you need to be careful if your script might emit characters that are special to make (the $ basically).

Upvotes: 1

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