CODEWITHSUNDEEP
vulkan
Andrew Tomazos
Andrew Tomazos

Reputation: 68618

VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT VkAccessFlags set to 0?

In the Vulkan spec it defines:

VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT is equivalent to VK_PIPELINE_STAGE_ALL_COMMANDS_BIT with VkAccessFlags set to 0 when specified in the second synchronization scope, but specifies no stages in the first scope.

and similarly:

VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT is equivalent to VK_PIPELINE_STAGE_ALL_COMMANDS_BIT with VkAccessFlags set to 0 when specified in the first synchronization scope, but specifies no stages in the second scope.

I'm unclear what it means by "with VkAccessFlags set to 0" in this context?

Technically VkAccessFlags is a type, not a variable, so it can't be set to anything.

(It seems to be adjusting the definitions of TOP/BOTTOM_OF_PIPE for some special property of VK_PIPELINE_STAGE_ALL_COMMANDS_BIT with respect to VkAccessFlags, but I can't quite see what that special property is or where it is specified.)

Anyone know what it's talking about?

(or, put another way: If we removed those two utterances of "with VkAccessFlags set to 0" from the spec, what would break?)

Upvotes: 1

Views: 1185

Answers (1)

krOoze
krOoze

Reputation: 13246

It is roundabout way to say the interpretation of the stage flag is different for a memory dependency.

For execution dependency in src it takes the stage bits you provide, and logically-earlier stages are included automatically. Similarly for dst, logically-later stages are included automatically.

But this applies only to the execution dependency. For a memory dependency, only the stage flags you provide count (and none are added automatically).

For example, let's say you have VK_PIPELINE_STAGE_ALL_COMMANDS_BIT + VK_ACCESS_MEMORY_WRITE_BIT in src. That means all memory writes from all previous commands will be made available. But if you have VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT + VK_ACCESS_MEMORY_WRITE_BIT in src, that means all memory writes from only BOTTOM_OF_PIPE stage are made available, so no memory writes are made available (because that particular stage doesn't make any).

Either way IMO, for code clarity it is better to always state all pipeline stages explicitly whenever one can.

Upvotes: 3

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