CODEWITHSUNDEEP
verilogsystem-verilog
Na Ja
Na Ja

Reputation: 21

For loop with binary numbers

I want to use a for loop in Verilog to get from binary 0000000 to 0011111. I have a problem with the increment part of the for loop. How should I exactly move to get to the 0011111?

I tried the following code, but it gives me an error.

for(DATA_IN=7'b0000000; DATA_IN<=7'b0011111; 1<<DATA_IN);

Upvotes: 1

Views: 1517

Answers (1)

toolic
toolic

Reputation: 62037

The expression 1<<DATA_IN is illegal syntax for the for_step part of the for loop. Typically, you need to make an assignment to the iterator variable: DATA_IN=... Refer to IEEE Std 1800-2017, section 12.7.1 The for-loop.

For example, to increment by 1 each time through the loop, use DATA_IN=DATA_IN+1. Here is a self-contained example:

module tb;

reg [7:0] DATA_IN;

initial begin
    for (DATA_IN=7'b0000000; DATA_IN<=7'b0011111; DATA_IN=DATA_IN+1) begin
        $displayb(DATA_IN);
    end
end

endmodule

Output:

00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
00010000
00010001
00010010
00010011
00010100
00010101
00010110
00010111
00011000
00011001
00011010
00011011
00011100
00011101
00011110
00011111

Upvotes: 2

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