CODEWITHSUNDEEP
chisel
mbrandalero
mbrandalero

Reputation: 416

Chisel and Timing Constraints files

Apologies in advance for the perhaps stupid question. Is it possible to integrate into the CHISEL flow a Scala script that generate timing constraint specifications (SDC) for a given design? e.g. press a button and you get your CHISEL design converted to Verilog along with an SDC file, ready for synthesis.

I currently have such a toolflow in place for VHDL (using python to generate the constraints files). But in VHDL the naming conventions are quite clear, not so sure about the CHISEL backend (also I couldn't find any reference on the web doing this)

Is it possible, or this is just not how CHISEL was intended to be used ?

Thanks in advance !

Upvotes: 2

Views: 205

Answers (1)

Jack Koenig
Jack Koenig

Reputation: 6065

Chisel has an annotation system to support tracking and linking against signals in the emitted Verilog. I've described this system in a previous question here on StackOverflow: Chisel: getting signal name in final Verilog

There is existing work to leverage this support and build physical design flows, see Hammer which is used by Chipyard.

Upvotes: 2

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