CODEWITHSUNDEEP
assemblyarmmemory-addressarm64cpu-cache
Chan Kim
Chan Kim

Reputation: 5919

Is there non-cacheable (=cache-bypass) load or store instruction for aarch64?

In sparc architecture, there is ASI (address space indicator) that is passed to load, store instruction so if ASI is 0x20, cache is bypassed like it's IO access. Even if the memory range is set to cacheable at the page table, cache is bypassed. This is sometime very convenient like when synchronizing between cores using variable, etc.
Is there something similar in aarch64 architecture? I've looked through the instruction content but couldn't find any in the load/store instruction list.

Upvotes: 2

Views: 2341

Answers (1)

user3124812
user3124812

Reputation: 1976

ARMv8 does not have such instructions. Load/Store instructions access memory depends on mapping attributes.

Mentioned LDNP and STNP instructions are not intended to by-pass cache.

The Load/Store Non-temporal Pair instructions provide a hint to the memory system that an access is non-temporal or streaming, and unlikely to be repeated in the near future. This means that data caching is not required. However, depending on the memory type, the instructions might permit memory reads to be preloaded and memory writes to be gathered to accelerate bulk memory transfers. (Arm Architecture Reference Manual)

So cache still might be involved.


On top of that Cortex-A53 TRM, for example, explicitly states that cache would be involved.

Non-temporal loads
Cache requests made by a non-temporal load instruction (LDNP) are allocated to the L2 cache only. The allocation policy makes it likely that the line is replaced sooner than other lines.

For cores syncronisation you might check ARMv8 manual for lock implementations (aka atomic) and spin-lock.

As a side note, check your chip documentation. Plenty of modern chips have special hardware capabilities to provide hardware based cache-coherent interfaces.

Upvotes: 6

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