CODEWITHSUNDEEP
verilogxilinxxilinx-ise
Bossman Flag
Bossman Flag

Reputation: 3

Simple code yielding error even though syntax seems correct (ISE VERILOG)

I am relatively very new(just a few hours old) in Xilinx ISE verilog coding. This is my code from my uni project. And it shows syntax error on the count = 0 line. I dont see anything wrong here upon running check syntax. How do i fix this?

 module syncdown(clk,rst,count);
input clk,rst;
output reg [3:0] count = 1;
always @(posedge clk);
begin
if(rst)
count = 0; // wrong here 
else
count = count-1;
end
endmodule

The error

ERROR:HDLCompiler:806 - "/home/bossman/mux/syncdown.v" Line 8: Syntax error near "=".

Upvotes: 0

Views: 44

Answers (1)

mkayaalp
mkayaalp

Reputation: 2716

Remove the semicolon at the end of the always line:

module syncdown(clk,rst,count);
input clk,rst;
output reg [3:0] count = 1;
always @(posedge clk)
begin
if(rst)
count = 0; // wrong here 
else
count = count-1;
end
endmodule

Upvotes: 2

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