arm-linux-gnueabi-gcc bad instruction strhlo,strhhs Cortex-A9

Question

I'm very new to arm and i'm trying to compile code for arm (Cortex-A9) using arm-linux-gnueabi-gcc.

the only flags i use are: -mcpu=Cortex-A9 --static

In my code I wrote the following instructions:

strhlo r1,[sl,r0]

Which seems to work fine here in shellstorm assembler: http://shell-storm.org/online/Online-Assembler-and-Disassembler/?inst=strhlo+r1%2C%5Bsl%2Cr0%5D&arch=arm&as_format=inline#assembly

But for some reason arm-linux-gnueabi-gcc won't compile them:

my_file.s:196: Error: bad instruction `strhlo r1,[sl,r0]'

Am I missing something?

Answer 1

so.s

strhlo r1,[sl,r0]

try with gcc

arm-none-eabi-gcc -mcpu=cortex-a9 so.s -o so.o
so.s: Assembler messages:
so.s:5: Error: bad instruction `strhlo r1,[sl,r0]'

try with gas

arm-none-eabi-gcc -mcpu=cortex-a9 so.s -o so.o
so.s: Assembler messages:
so.s:5: Error: bad instruction `strhlo r1,[sl,r0]'

remove the conditional and the halfword

str r1,[sl,r0]

arm-none-eabi-gcc -c -mcpu=cortex-a9 so.s -o so.o
arm-none-eabi-objdump -d so.o

so.o:     file format elf32-littlearm


Disassembly of section .text:

00000000 <.text>:
   0:   e78a1000    str r1, [sl, r0]

Now add the conditional

strlo r1,[sl,r0]

arm-none-eabi-gcc -c -mcpu=cortex-a9 so.s -o so.o
arm-none-eabi-objdump -d so.o

so.o:     file format elf32-littlearm


Disassembly of section .text:

00000000 <.text>:
   0:   e78a1000    str r1, [sl, r0]

assembly language is specific to the assembler not the target, so what if we put the halfword after the conditional not before.

strloh r1,[sl,r0]

arm-none-eabi-gcc -c -mcpu=cortex-a9 so.s -o so.o
arm-none-eabi-objdump -d so.o

so.o:     file format elf32-littlearm


Disassembly of section .text:

00000000 <.text>:
   0:   318a10b0    strhcc  r1, [sl, r0]

Now if you had inlined this or this were thumb code then let's see what happens, maybe it works:

.thumb
.syntax unified
strloh r1,[sl,r0]

arm-none-eabi-gcc -c -mcpu=cortex-a9 so.s -o so.o
so.s: Assembler messages:
so.s:4: conditional infixes are deprecated in unified syntax
so.s:4: Error: thumb conditional instruction should be in IT block -- `strloh r1,[sl,r0]'

So that is a different error message. Which you may still run into before this is all over.

In this case it was an assembly language thing the arm assemblers (there are many from arm over the decades) might accept strhlo, but GNU assembler and gcc apparently don't. Again the language is defined by the tool (gcc/gas) not the target (arm/thumb).

The first thing that jumped out from your question is gcc, cortex-a9 (meaning armv7-a) and that means thumb mode by default (at times difficult to get it to generate arm code). Granted you are possibly using gcc to get at GNU assembler rather than just going to gnu assembler directly, but there was no minimal example shown (as you can see one line of code is all it takes to see what is going wrong).

---

As mentioned in the comments:

.thumb
.syntax unified
strh r1,[sl,r0]

Disassembly of section .text:

00000000 <.text>:
   0:   f82a 1000   strh.w  r1, [sl, r0]

The arm version of the unconditional instruction starts with 0xE and the thumb2 version starts with 0xF, making it easy to figure out which mode...

Answer 2

Which GCC version are you using?

In old syntax, the condition codes are put between the instruction and its suffix of load/store instructions like:

ldmneia
ldreqd
strneb

Maybe you should try strloh instead of strhlo