CODEWITHSUNDEEP
verilog
naazz
naazz

Reputation: 33

I am using define statement, but when I run the code, it says the variable is not declared

I have 16-bit instructions depending upon the 5-bit opcode field, 27-bit control signals are generated. I have defined these 27-bit values to its corresponding instruction word. The code is attached below. When I run this code it says SW is not declared.

`define NOP 27'b 000000000000000000000000000
`define SSS 27'b 000000000000000000010000000
`define SSN 27'b 000000000000000000100000000
`define SM 27'b 000000000000000001000000000
`define SW 27'b000000000000000010000000000
module top_module(
    input system_clk, 
    input [15:0] address,
    output [15:0] instruction,
    output [26:0] control_signal,
    output reg [7:0] LoadReg
    );
instruction_memory im(
.address(address),
.instruction(instruction)
);
instruction_decoder id(
.instr_in(instruction),
.cntrl_out(control_signal)
);

always@(posedge system_clk)
    begin
        case(control_signal)
        SW: LoadReg <= instruction[7:0]; 
        endcase
    end
endmodule

Upvotes: 2

Views: 579

Answers (1)

toolic
toolic

Reputation: 62037

When you declare a define macro, you don't need to use the backtick, but when you use the macro you need to add the backtick. Change:

    SW: LoadReg <= instruction[7:0];

to:

    `SW: LoadReg <= instruction[7:0];

Upvotes: 2

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