CODEWITHSUNDEEP
verilogsystem-verilog
Gus
Gus

Reputation: 4505

Concatenation in output of module

When I instantiate a module and I only care about some of the bits in the output, is there a short-hand syntax to throw away the bits? Something like

my_module module_instance
( 
 .some_output({garbage1,important1[7:0]})
);

In this case, the signal some_output in my_module is 9 bits wide, but I only want to stick the lower 8 bits into important1. I could make a signal with all 9 bits, and then just select the 8 from it, and I know the compiler will optimize it, but I'm looking for an idiom or an abbreviation.

Upvotes: 2

Views: 4252

Answers (2)

Andy
Andy

Reputation: 4866

One option is to parameterize the module, as toolic suggests. If you're stuck with the wide port, I'm not aware of any seamless way to discard the extra bits.

Using 1'bz for the unused bits is tempting, but isn't legal.

If the unused bits are the MSBs, you can connect a 9-bit port to an 8-bit signal, but this is poor coding style and will result in warnings from some tools.

One possibility is to define a convention for unused signals, for example, a suffix of _NC (no-connect). This will help document the intention. You may also be able to filter any warnings about the dangling signal using a pattern match rather than listing the signals individually.

Another possibility, especially if you adopt a coding style where signals are not renamed as they are passed through ports, is to keep the full width of the signal through the port and trim the extra bits elsewhere.

Upvotes: 1

toolic
toolic

Reputation: 62037

If you parameterize the width of the output port in your module, then pass the parameter to the instance, there is no need to create a signal to throw away unused bits:

my_module module_instance #(.WIDTH(8))
( 
 .some_output(important1[7:0])
);

Upvotes: 3

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