CODEWITHSUNDEEP
assemblymemory-alignmentriscv
Rathish
Rathish

Reputation: 11

RISC V RAM address alignment for SW,SH,SB

I am implementing a RISC V rv32i in verilog HDL.

In RAM access, currently I designed an 8-bit wide RAM. Hence for writing and reading 1 word 4 locations are read in 1 cycle. Similarly 2 locations read for halfword and 1 for byte.

This was done under the impression that addresses to store byte can be 1 byte aligned and addresses to store halfword is 2 byte aligned. Though this works in simulation, this results in an unsynthesisable design. Hence, I am trying to redesign the RAM controller.

In my new design, the width of 32 will synthesize, but if a halfword is written to 0x8004 then 0x8006 will not be usable. Can we assume that all addresses to memory are 4 byte aligned? Or does it vary between SW,SH,SB?

Will this arrangement break RISC-V compliance?

Upvotes: 1

Views: 5006

Answers (1)

Erik Eidt
Erik Eidt

Reputation: 26636

The concept of alignment is dependent upon the size of data.  There is no concept of alignment for byte sized data, any byte is potentially accessible (we could say all byte addresses are aligned).  For half word (2 byte) data, an address is either even (aligned) or odd (misaligned).  For word data the address is either multiple of 4 (aligned) or it is misaligned.

RISC V requires that instructions are properly aligned but this is not the case for data words.  However, a legal implementation may perform exceptionally slowly for misaligned accesses.  In other words, you can make an implementation that faults (take an exception) on misaligned access, as long as there is a software exception handler that can perform the misaligned access, even if the software exception handler is 100x slower than for aligned addresses.

From https://inst.eecs.berkeley.edu/~cs61c/sp19/lectures/lec05.pdf:

• RISC-V does not require that integers be word aligned...
  • But it is very very bad if you don't make sure they are...
• Consequences of unaligned integers
  • Slowdown: The processor is allowed to be a lot slower when it happens
    • In fact, a RISC-V processor may natively only support aligned accesses, and do unaligned-access in software!
    An unaligned load could take hundreds of times longer!
• Lack of atomicity: The whole thing doesn't happen at once... can introduce lots of very subtle bugs

However, users will expect aligned accesses to run full speed.  Every byte of a string should be accessible (as bytes), for example, so faulting (to a slow exception handler) on odd addresses for byte-sized access would be frowned upon.  The same goes for half words, every even address is expected to allow full performance; and for words, as 4 byte aligned addresses have the expectation of full performance.

Compilers can easily align data structures to prevent most cases of misalignment and will most likely do so for RISC V.  (Some compilers have directives to allow misalignment for packing data structures for size improvement traded off with performance.)

Upvotes: 2

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