CODEWITHSUNDEEP
javamakefile
Orbyfied
Orbyfied

Reputation: 154

Makefile: "multiple target patterns. stop."

Of course I am being stupid again.

Can anyone tell me why this;

$(shell compileJava.bat)

an expression without any variables, special characters, unwanted spaces, colons, etc. is causing error Makefile:70: *** multiple target patterns. Stop..

I've searched the whole internet for an answer.

What I am trying to do.

I'm making a Java project involving natives. I have the structure like this;

+ root (project)
  -+ build
     -+ natives (for the built native libraries like dlls)
     -+ classes (for the built java classes)
     -+ generated (gradles compileJava task automatically generates jni header files)
  -+ src
    -+ main
      -+ java (all of the java source)
      -+ resources
      -+ c
        -+ Makefile (will be called to compile and link the c(++) code)
  -+ Makefile (the general makefile, error occurs in here at line 70)
  -+ compileJava.bat (calls gradlew compileJava with a jdk argument, but since im using 
      windows and make doesnt support colons, like C:, i had to put it in a batch file)

and the root Makefile is supposed to follow this procedure;

[1] call "compileJava.bat" to compile the java code & gen the headers (error occurs here)
[2] call "make -C src/main/c" to run the native build makefile
[3] call "jar cf <name> <contents>" to package all java code (and the natives) into a jar

Links

My whole root Makefile: Pastebin

compileJava.bat: Pastebin

Upvotes: 0

Views: 598

Answers (1)

MadScientist
MadScientist

Reputation: 100836

What does $(shell ...) do? It invokes a shell command, and it evaluates to the standard output of the command.

If you write a makefile like this:

$(shell true)

then the shell command prints nothing and so it expands to nothing, then make tries to evaluate nothing, and nothing happens.

If you write a makefile like this:

$(shell echo hi)

Then the shell comand prints "hi", and this function expands to the string "hi", so it's as if you wrote a makefile:

hi

and that, of course, is not a valid makefile.

So this:

$(shell make -C src/...)

expands to the entire output of running make which is obviously not a valid makefile at all.

You can avoid this by putting the results in a variable:

_tmp := $(shell make -C src/...)

But, I really think you need to rethink your whole approach. Makefiles are not procedural programs like shell scripts.

Upvotes: 2

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