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synthesisyosys
Donghui Li
Donghui Li

Reputation: 23

Why Yosys synthesis the sequential statement to constant

I have the Verilog statement below:

module test (A,B, CLK);
input  A, CLK;
output B;

    always@(posedge CLK) 
        if(A) B <= 1'b1;

endmodule

I am expecting a register. However, after I synthesis it with Yosys, I got the result as follow:

assign B = 1'b1;

I don't understand why Yosys translate the above Verilog statement to a constant 1.

Please advice, thanks!

Upvotes: 2

Views: 501

Answers (2)

ToTamire
ToTamire

Reputation: 1703

Your B has two possible values:

  • 1'b x during initialization (more in IEEE Std 1364 4.2.2 Variable declarations),
  • 1'b 1 when A is equal to 1'b 1.

You really have only one value. Thats mean you can optimize it to hardwired 1'b 1.

This is not a Yosys fault. All (or almost all) synthesis software will behave same way. If you want to let it work (if I guess what you want), you have to allow B to take two different values. You can do it by initial value equal to 1'b 0 or by reset to value 1'b 0.

I suggest to use reset instead of initial value because initial value can be implemented as A connected to register's set pin.

Upvotes: 1

Paul Horsfall
Paul Horsfall

Reputation: 8192

Interesting! I noticed that if you assign an initial value of zero to the register (e.g. output reg B = 1'b0) you do get a flip-flop. (I used read_verilog <your_code.v> ; synth ; show.)

However, an initial value of one still produces the constant output you mention. So perhaps what's happening here (and I'm only speculating) is that when an initial value is not given, yosys is free to pick its own, in which case it picks 1'b1, so that the whole circuit is equivalent to a simple hard-wired constant? Only when the initial value is zero is the flip-flop necessary?

Upvotes: 0

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