CODEWITHSUNDEEP
verilogsystem-verilogverificationtest-bench
d4mb
d4mb

Reputation: 33

System Verilog Testbench Regression Run

Can someone explain to me what is meant with a "Regression Run"? I already googled for at least 3 hours, but I still don't really get it.

Upvotes: 1

Views: 1357

Answers (1)

toolic
toolic

Reputation: 62037

A regression run typically means that you run Verilog simulations on a group of tests to verify that your design works properly.

If you have a small design, such as a single flip-flop, your testbench might only have a single test. But, once you have a larger design, like a UART, then your testbench will likely have several tests. Each test would exercise a major mode of operation: receive-only, transmit-only, simultaneous transmit and receive, varying baud rates, etc. Your testbench must be self-checking, and each test should either pass or fail.

As you develop your design code, adding new features, you would periodically run simulations on all your tests to make sure you have not inadvertently broken other parts of the design. Running these tests is commonly referred to as running a regression. You expect tests to pass, but if any test fails, then you need to rethink your most recent design changes.

This is also known as Regression testing.

Another reference.

Upvotes: 1

Related Questions