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verilogcomparator
Juan Diego
Juan Diego

Reputation: 25

Verilog Two bit Magnitude comparator

I was trying to write Verilog code of a two bit comparator, but I keep getting errors. Any help?

Error Codes:

10170 Verilog HDL syntax error at two_bitcomparatorVerilog.v(5) near text: ";"; expecting ")"

10170 Verilog HDL syntax error at two_bitcomparatorVerilog.v(7) near text: ";"; expecting ")"

10170 Verilog HDL syntax error at two_bitcomparatorVerilog.v(15) near text: "~"; expecting ")"

Design:

module twobit_comparator(

    //assigning inputs
    input wire [1:0] A, B;
    // assigning outputs
    output wire LT, GT, EQ;
    // L=Less, G=Greater, E=Equal 
    );
    
    
    wire [9:0] s;
    
    //A = B output 
    assign s0 = (~A[1] & ~A[0] & ~B[1] ~B[0]);
    assign s1 = (~A[1] & A[0] & ~B[1] & B[0]);
    assign s2 = (A[1] & ~A[0] & B[1] & ~B[0]);
    assign s3 = (A[1] & A[0] & b[1] & B[0]);
    assign EQ = s0 | s1 | s2 | s3;
    
    //A less than B output 
    assign s4 = (~A[0]) & (~A[1]) & B[0];
    assign s5 = (~A[1]) & B[1];
    assign s6 = (~A[0]) & B[1] & B[0];
    assign LT = s4 | s5| s6;
    
    // A greater than B output
    assign s7 = (~B[0]) & (~B[1]) & A[0];
    assign s8 = (~B[1]) &  A[1];
    assign s9 = (~B[0]) & A[1] & A[0];
    assign GT = s7 | s8 | s9;
    
endmodule

Upvotes: 1

Views: 1658

Answers (1)

toolic
toolic

Reputation: 62164

Separate ports with commas, not semicolons, and do not end the port list with a semicolon:

module twobit_comparator(

//assigning inputs
input wire [1:0] A, B,
// assigning outputs
output wire LT, GT, EQ
// L=Less, G=Greater, E=Equal 
);

You are missing the & operator; I added it here:

assign s0 = (~A[1] & ~A[0] & ~B[1] & ~B[0]);
//                                 ^

I changed b to B here (Verilog is case-sensitive):

assign s3 = (A[1] & A[0] & B[1] & B[0]);
//                         ^

I don't get any more compile errors with the changes above. However, you declared signal s, but it is not used. And, you did not declare s0, s1, etc., but you are using them. This works because Verilog allows you to use undeclared wires when they are 1-bit wide. But, you should declare all signals. For example, you could use:

wire [9:0] s;

assign s[0] = (~A[1] & ~A[0] & ~B[1] & ~B[0]);
assign s[1] = (~A[1] & A[0] & ~B[1] & B[0]);

Upvotes: 2

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