CODEWITHSUNDEEP
stm32flash-memory
Guillaume Petitjean
Guillaume Petitjean

Reputation: 2718

What is the benefit of DDR versus SDR in the QSPI protocol?

I'm developping a driver for a QSPI Serial Flash connected to a STM32H753. I'm used to SPI but not so much to QSPI.

I don't understand the benefit of Double Data Rate versus Single Data Rate. Of course I understand DDR allows to transmit two bits instead of one per SCK clock cycle. but at the end, isn't the limit in data bandwith identical in both modes ?

For example for my component (see SDR QuadRead vs. DDR QuadRead):

enter image description here

The maximum read rate is the same in SDR or DDR, the only difference being SCK signal frequency. But the master and the slave still need to support a frequency twice higher for IO than for SCK.

The only difference I've found is that the Instruction phase is twice slower than the data phase in DDR:

enter image description here

Any idea ?

Upvotes: 2

Views: 3004

Answers (3)

vjalle
vjalle

Reputation: 973

DDR might make no sense with your flash device, but might double the bandwidth with other QSPI devices. For example, with HyperRAM. They're very fast, certainly the serial communication is the bottleneck.

In your situation I'd try DDR anyway, because EMI and power dissipation might be sightly better. Or you can go with SDR too, that's more compatible. Not all devices support DDR.

Upvotes: 0

Serval
Serval

Reputation: 163

If there is no special reason, such as the clock maximum support rate can not reach. It is recommended to use SDR. Because DTR's Controller design is more complex, not as simple and stable as SDR.

Upvotes: 0

0___________
0___________

Reputation: 68034

but at the end, isn't the limit in data bandwith identical in both modes

the only difference being SCK signal frequency.

And it is very important for many reasons. We try to reduce those frequencies as much as possible as it simplifies the PCB design (especially more complicated ones), reduces the EMI (and commercial devices usually have to pass certification). The added noise affects analog part of the PCB/uC reducting for example quality of ADC.

So having on the bus 54MHz instead of 108MHz is a great benefit (remember that all data lines (and we can have 8 in octaSPI) also work with higher frequencies, additionally complicating the device design.

Upvotes: 1

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