Case statement doesn't seem to be working

Question

The value of oV should be the value on the right side in the StateToCountSequence that corresponds to the respective iState value on the left. However, oV only seems to be able to have the values 2 or 3, as shown the in capture below.

Does anyone know what I should do about this?

module CounterSkipReverse(iClk, iRst, iSkip, iRev, oState);
   input iClk, iRst, iSkip, iRev;
   //declare oState:
    output integer oState;
   //declare internal wires and reg types here:
    always @ (posedge iClk) begin
        if (iRst == 1)
            oState <= 0;
        else
            if (iSkip == 0 & iRev == 0) oState <= oState + 4'd1;
            else if (iSkip == 1 & iRev == 0) oState <= oState + 4'd5;
            else if (iSkip == 0 & iRev == 1) oState <= oState - 4'd1;
            else if (iSkip == 1 & iRev == 1) oState <= oState + 4'd9;
            if (oState < 0) oState <= oState + 4'd14;
            if (oState > 14) oState <= oState - 4'd14;
    end 
 
endmodule
 
module StateToCountSequence(iState, oV);
    //declare the input and output 
    input iState;
    output reg [3:0]oV;
  
    //declare any internal wire and reg types here.
    
    always @ (iState) begin
        case(iState)
            4'd0: oV = 4'd3;
            4'd1: oV = 4'd2;
            4'd2: oV = 4'd4;
            4'd3: oV = 4'd9;
            4'd4: oV = 4'd9;
            4'd5: oV = 4'd0;
            4'd6: oV = 4'd7;
            4'd7: oV = 4'd1;
            4'd8: oV = 4'd1;
            4'd9: oV = 4'd5;
            4'd10: oV = 4'd1;
            4'd11: oV = 4'd7;
            4'd12: oV = 4'd0;
            4'd13: oV = 4'd8;
            4'd14: oV = 4'd9;
        endcase
    end
  
    //Have you checked for inferred latches in this module?
endmodule 

module CompleteCounter(iClk, iRst, iSkip, iRev, oV, oState);
    input iClk, iRst, iSkip, iRev;
    output [3:0] oV;
    //declare oState next line
    output [3:0]oState;
    
    CounterSkipReverse cntr(.iClk(iClk), .iRst(iRst), .iSkip(iSkip), .iRev(iRev), .oState(oState));
    StateToCountSequence statemap(.iState(oState), .oV(oV));
endmodule

`timescale 1ns / 1ps
module AssignmentTestBench;
 
   //declare internal signals and instantiate module CompleteCounter.
    reg iClk, iRst, iSkip, iRev;
    wire [3:0]oState;
    wire [3:0]oV;
    
    initial begin
        iClk = 1'b1;
        iRst = 0;
        iSkip = 0;
        iRev = 0;
    end
    
    CompleteCounter counter(iClk, iRst, iSkip, iRev, oV, oState);
    
   //generate test sequences for all state transitions
    always begin
        #5 iClk = ~iClk;  //period 10 ns for clock
    end
    
    always begin  // control w input and reset
        #1;
        
        // iSkip = 0, iRev = 0
        #10 iRst = 1'b1;
        #10 iRst = 1'b0;
        #300;  // 30 clock cycles
        
        // iSkip = 1, iRev = 0
        #10 iRst = 1'b1;
        #10 iRst = 1'b0;
            iSkip = 1'b1;
        #80;
        
        // iSkip = 1, iRev = 1
        #10 iRst = 1'b1;
        #10 iRst = 1'b0;
            iRev = 1'b1;
        #40;
        
        // iSkip = 0, iRev = 1
        #10 iRst = 1'b1;
        #10 iRst = 1'b0;
            iSkip = 1'b0;
        #150;

        $display("Finished test");
        $finish;  // remove for modelsim
        $stop;
    end
  
endmodule

Answer 1

The signal iState is a 1-bit signal in the StateToCountSequence, which means it can only take on the known values 0 and 1. Thus, you can only set oV to 3 and 2.

Change:

input iState;

to:

input [3:0] iState;